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msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 1 post office box 655303 ? dallas, texas 75265 low supply-voltage range, 1.8 v to 3.6 v ultralow-power consumption: ? active mode: 280 a at 1 mhz, 2.2 v ? standby mode: 1.1 a ? off mode (ram retention): 0.1 a five power saving modes wake-up from standby mode in less than 6 s 16-bit risc architecture, 125-ns instruction cycle time 12-bit a/d converter with internal reference, sample-and-hold and autoscan feature 16-bit timer_b with three ? or seven ? capture/compare-with-shadow registers 16-bit timer_a with three capture/compare registers on-chip comparator serial communication interface (usart), select asynchronous uart or synchronous spi by software: ? two usarts (usart0, usart1) ? ? one usart (usart0) ? brownout detector supply voltage supervisor/monitor with programmable level detection serial onboard programming, no external programming voltage needed programmable code protection by security fuse integrated lcd driver for up to 160 segments bootstrap loader family members include: ? msp430f435, msp430f4351 : 16kb+256b flash memory, 512b ram ? msp430f436, msp430f4361 : 24kb+256b flash memory, 1kb ram ? msp430f437, msp430f4371 : 32kb+256b flash memory, 1kb ram ? msp430f447: 32kb+256b flash memory, 1kb ram ? msp430f448, msp430f4481 : 48kb+256b flash memory, 2kb ram ? msp430f449, msp430f4491 : 60kb+256b flash memory, 2kb ram for complete module descriptions, see the msp430x4xx family user?s guide , literature number slau056 ? msp430f43x, and msp430f43x1 devices ? msp430f44x, and msp430f44x1 devices the msp430f43x1 and msp430f44x1 devices are identical to the msp430f43x and msp430f44x devices, respectively ? with the exception that the adc12 module is not implemented. description the texas instruments msp430 family of ultralow power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. the architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. the devices feature a powerful 16-bit risc cpu, 16-bit registers, and constant generators that contribute to maximum code efficiency. the digitally controlled oscillator (dco) allows wake-up from low-power m odes to active mode in less than 6 s. this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. these devices have limited built-in esd protection. production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. copyright ? 2009, texas instruments incorporated please be aware that an important notice concerning avail ability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 2 post office box 655303 ? dallas, texas 75265 description (continued) the msp430x43x(1) and the msp430x44x(1) series are microcontroller configurations with two built-in 16-bit timers, a fast 12-bit a/d converter (not implemented on the msp430f43x1 and msp430f44x1 devices), one or two universal serial synchronous/asynchronous communication interfaces (usar t), 48 i/o pins, and a liquid crystal driver (lcd) with up to 160 segments. typical applications include sensor systems that capture analog signals, convert them to digital values, and process and transmit the data to a host system, or process this data and display it on a lcd panel. the timers make the configurations ideal for industrial control applications such as ripple counters, digital motor control, ee-meters, hand-held meters, etc. the hardware multiplier enhances the performance and offers a broad code and hardware-compatible family solution. available options packaged devices t a plastic 80-pin qfp (pn) plastic 100-pin qfp (pz) ?40 c to 85 c msp430f435ipn msp430f436ipn msp430f437ipn msp430f4351ipn msp430f4361ipn msp430f4371ipn msp430f435ipz msp430f436ipz msp430f437ipz msp430f4351ipz msp430f4361ipz msp430f4371ipz msp430f447ipz msp430f448ipz msp430f449ipz MSP430F4481IPZ msp430f4491ipz ? for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti web site at www.ti.com. ? package drawings, thermal data, and symbolization are available at www.ti.com/packaging. development tool support all msp430 microcontrollers include an embedded emulation module (eem) allowing advanced debugging and programming through easy to use development tools. recommended hardware options include the following: debugging and programming interface ? msp-fet430uif (usb) ? msp-fet430pif (parallel port) debugging and programming interface with target board ? msp-fet430u100 (pz package) stand-alone target board ? msp-ts430pz100 (pz package) production programmer ? msp-gang430
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 3 post office box 655303 ? dallas, texas 75265 pin designation, msp430x4351ipn, msp430x4361ipn, msp430x4371ipn 22 23 p1.7/ca1 p2.0/ta2 p2.1/tb0 p2.2/tb1 p2.3/tb2 p2.4/utxd0 p2.5/urxd0 dv ss2 dv cc2 p5.7/r33 p5.6/r23 p5.5/r13 r03 p5.4/com3 p5.3/com2 p5.2/com1 com0 p3.0/ste0/s31 p3.1/simo0/s30 p3.2/somi0/s29 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 dv cc1 p6.3 p6.4 p6.5 p6.6 p6.7/svsin reserved xin xout dv ss dv ss p5.1/s0 p5.0/s1 p4.7/s2 p4.6/s3 p4.5/s4 p4.4/s5 p4.3/s6 p4.2/s7 p4.1/s8 25 26 27 28 pn package (top view) tdo/tdi 79 78 77 76 75 80 74 p6.1 p6.0 rst/nmi tck tms p2.6/caout/s19 s21 s15 s16 s17 72 71 70 73 29 30 31 32 33 69 68 21 p4.0/s9 xt2out 67 66 65 64 34 35 36 37 s22 s23 p3.7/s24 p3.6/s25 p1.0/ta0 p1.1/ta0/mclk p1.2/ta1 p1.3/tbouth/svsout p3.5/s26 p3.4/s27 38 39 40 p1.4/tbclk/smclk p1.5/taclk/aclk 63 62 61 tdi/tclk xt2in p1.6/ca0 s10 s20 p3.3/uclk0/s28 s11 s12 s13 s14 p2.7/s18 p6.2 msp430f4351ipn msp430f4361ipn msp430f4371ipn ss1 dv cc av ss av
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 4 post office box 655303 ? dallas, texas 75265 pin designation, msp430x4351ipz, msp430x4361ipz, msp430x4371ipz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 p1.7/ca1 p6.1 p6.0 rst/nmi xt2in xt2out p1.3/tbouth/svsout p1.4/tbclk/smclk p1.5/taclk/aclk p1.6/ca0 p2.3/tb2 s14 s15 s16 s17 s18 s20 s25 s26 s27 s28 s29 s31 p4.7/s34 s30 pz package (top view) p1.0/ta0 tdi/tclk tdo/tdi s21 ss1 dv p6.2 p1.2/ta1 s24 p4.6/s35 dv cc1 p6.3 p6.4 p6.5 p6.6 p6.7/svsin reserved xin xout dv ss dv ss p5.1/s0 p5.0/s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 p2.4/utxd0 p2.5/urxd0 p2.6/caout p2.7 p3.0/ste0 p3.1/simo0 p3.2/somi0 p3.3/uclk0 p3.4 p3.5 p3.6 p3.7 p4.0 p4.1 dv ss2 dv cc2 p5.7/r33 p5.6/r23 p5.5/r13 r03 p5.4/com3 p5.3/com2 p5.2/com1 com0 p4.2/s39 s19 s22 s23 s33 s32 p4.5/s36 p4.4/s37 p4.3/s38 cc av ss av tck tms p1.1/ta0/mclk p2.0/ta2 p2.1/tb0 p2.2/tb1 msp430f4351ipz msp430f4361ipz msp430f4371ipz
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 5 post office box 655303 ? dallas, texas 75265 pin designation, msp430x435ipn, msp430x436ipn, msp430x437ipn 22 23 p1.7/ca1 p2.0/ta2 p2.1/tb0 p2.2/tb1 p2.3/tb2 p2.4/utxd0 p2.5/urxd0 dv ss2 dv cc2 p5.7/r33 p5.6/r23 p5.5/r13 r03 p5.4/com3 p5.3/com2 p5.2/com1 com0 p3.0/ste0/s31 p3.1/simo0/s30 p3.2/somi0/s29 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 dv cc1 p6.3/a3 p6.4/a4 p6.5/a5 p6.6/a6 p6.7/a7/svsin vref+ xin xout veref+ vref?/veref? p5.1/s0 p5.0/s1 p4.7/s2 p4.6/s3 p4.5/s4 p4.4/s5 p4.3/s6 p4.2/s7 p4.1/s8 25 26 27 28 pn package (top view) tdo/tdi 79 78 77 76 75 80 74 p6.1/a1 p6.0/a0 rst/nmi tck tms p2.6/caout/s19 s21 s15 s16 s17 72 71 70 73 29 30 31 32 33 69 68 21 p4.0/s9 xt2out 67 66 65 64 34 35 36 37 s22 s23 p3.7/s24 p3.6/s25 p1.0/ta0 p1.1/ta0/mclk p1.2/ta1 p1.3/tbouth/svsout p3.5/s26 p3.4/s27 38 39 40 p1.4/tbclk/smclk p1.5/taclk/aclk 63 62 61 tdi/tclk xt2in p1.6/ca0 s10 s20 p3.3/uclk0/s28 s11 s12 s13 s14 p2.7/adc12clk/s18 p6.2/a2 msp430f435ipn msp430f436ipn msp430f437ipn ss1 dv cc av ss av
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 6 post office box 655303 ? dallas, texas 75265 pin designation, msp430x435ipz, msp430x436ipz, msp430x437ipz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 p1.7/ca1 p6.1/a1 p6.0/a0 rst/nmi xt2in xt2out p1.3/tbouth/svsout p1.4/tbclk/smclk p1.5/taclk/aclk p1.6/ca0 p2.3/tb2 s14 s15 s16 s17 s18 s20 s25 s26 s27 s28 s29 s31 p4.7/s34 s30 pz package (top view) p1.0/ta0 tdi/tclk tdo/tdi s21 ss1 dv p6.2/a2 p1.2/ta1 s24 p4.6/s35 dv cc1 p6.3/a3 p6.4/a4 p6.5/a5 p6.6/a6 p6.7/a7/svsin vref+ xin xout veref+ vref?/veref? p5.1/s0 p5.0/s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 p2.4/utxd0 p2.5/urxd0 p2.6/caout p2.7/adc12clk p3.0/ste0 p3.1/simo0 p3.2/somi0 p3.3/uclk0 p3.4 p3.5 p3.6 p3.7 p4.0 p4.1 dv ss2 dv cc2 p5.7/r33 p5.6/r23 p5.5/r13 r03 p5.4/com3 p5.3/com2 p5.2/com1 com0 p4.2/s39 s19 s22 s23 s33 s32 p4.5/s36 p4.4/s37 p4.3/s38 cc av ss av tck tms p1.1/ta0/mclk p2.0/ta2 p2.1/tb0 p2.2/tb1 msp430f435ipz msp430f436ipz msp430f437ipz
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 7 post office box 655303 ? dallas, texas 75265 pin designation, msp430x4481ipz, msp430x4491ipz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 p1.7/ca1 p6.1 p6.0 rst/nmi xt2in xt2out p1.3/tbouth/svsout p1.4/tbclk/smclk p1.5/taclk/aclk p1.6/ca0 p2.3/tb2 s14 s15 s16 s17 s18 s20 s25 s26 s27 s28 s29 s31 p4.7/s34 s30 pz package (top view) p1.0/ta0 tdi/tclk tdo/tdi s21 ss1 dv p6.2 p1.2/ta1 s24 p4.6/s35 dv cc1 p6.3 p6.4 p6.5 p6.6 p6.7/svsin reserved xin xout dv ss dv ss p5.1/s0 p5.0/s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 p2.4/utxd0 p2.5/urxd0 p2.6/caout p2.7 p3.0/ste0 p3.1/simo0 p3.2/somi0 p3.3/uclk0 p3.4/tb3 p3.5/tb4 p3.6/tb5 p3.7/tb6 p4.0/utxd1 p4.1/urxd1 dv ss2 dv cc2 p5.7/r33 p5.6/r23 p5.5/r13 r03 p5.4/com3 p5.3/com2 p5.2/com1 com0 p4.2/ste1/s39 s19 s22 s23 s33 s32 p4.5/uclk1/s36 p4.4/somi1/s37 4.3/simo1/s38 cc av ss av tck tms p1.1/ta0/mclk p2.0/ta2 p2.1/tb0 p2.2/tb1 MSP430F4481IPZ msp430f4491ipz
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 8 post office box 655303 ? dallas, texas 75265 pin designation, msp430x447ipz, msp430x448ipz, msp430x449ipz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 p1.7/ca1 p6.1/a1 p6.0/a0 rst/nmi xt2in xt2out p1.3/tbouth/svsout p1.4/tbclk/smclk p1.5/taclk/aclk p1.6/ca0 p2.3/tb2 s14 s15 s16 s17 s18 s20 s25 s26 s27 s28 s29 s31 p4.7/s34 s30 pz package (top view) p1.0/ta0 tdi/tclk tdo/tdi s21 ss1 dv p6.2/a2 p1.2/ta1 s24 p4.6/s35 dv cc1 p6.3/a3 p6.4/a4 p6.5/a5 p6.6/a6 p6.7/a7/svsin vref+ xin xout veref+ vref?/veref? p5.1/s0 p5.0/s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 p2.4/utxd0 p2.5/urxd0 p2.6/caout p2.7/adc12clk p3.0/ste0 p3.1/simo0 p3.2/somi0 p3.3/uclk0 p3.4/tb3 p3.5/tb4 p3.6/tb5 p3.7/tb6 p4.0/utxd1 p4.1/urxd1 dv ss2 dv cc2 p5.7/r33 p5.6/r23 p5.5/r13 r03 p5.4/com3 p5.3/com2 p5.2/com1 com0 p4.2/ste1/s39 s19 s22 s23 s33 s32 p4.5/uclk1/s36 p4.4/somi1/s37 4.3/simo1/s38 cc av ss av tck tms p1.1/ta0/mclk p2.0/ta2 p2.1/tb0 p2.2/tb1 msp430f447ipz msp430f448ipz msp430f449ipz
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 9 post office box 655303 ? dallas, texas 75265 msp430x43x1 functional block diagram comparator_ a dv cc1/2 dv ss1/2 av cc av ss rst /nmi p2 flash 32kb 24kb 16kb ram 1kb 512b watchdog timer wdt 15/16-bit port 2 8 i/o interrupt capability por/ svs/ brownout basic timer 1 1 interrupt vector lcd 128/160 segments 1,2,3,4 mux f lcd 8 mclk xout jtag interface xin smclk aclk mdb mab emulation p3 port 3 8 i/o 8 module timer_a3 3 cc reg p1 port 1 8 i/o interrupt capability 8 p5 port 5 8 i/o 8 p6 port 6 6 i/o 8 p4 port 4 8 i/o 8 timer_b3 3 cc reg shadow reg usart0 uart mode spi mode xt2in xt2out oscillator fll+ 8 mhz cpu incl. 16 registers msp430x43x functional block diagram comparator_ a dv cc1/2 dv ss1/2 av cc av ss rst /nmi p2 flash 32kb 24kb 16kb ram 1kb 512b watchdog timer wdt 15/16-bit port 2 8 i/o interrupt capability por/ svs/ brownout basic timer 1 1 interrupt vector lcd 128/160 segments 1,2,3,4 mux f lcd 8 mclk xout jtag interface xin smclk aclk mdb mab emulation p3 port 3 8 i/o 8 module timer_a3 3 cc reg p1 port 1 8 i/o interrupt capability 8 p5 port 5 8 i/o 8 p6 port 6 6 i/o 8 p4 port 4 8 i/o 8 timer_b3 3 cc reg shadow reg usart0 uart mode spi mode xt2in xt2out adc12 12-bit 8 channels <10 s conv. oscillator fll+ 8 mhz cpu incl. 16 registers
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 10 post office box 655303 ? dallas, texas 75265 msp430x44x1 functional block diagram comparator_ a dv cc1/2 dv ss1/2 av cc av ss rst /nmi p2 flash 60kb 48kb ram 2kb watchdog timer wdt 15/16-bit port 2 8 i/o interrupt capability por/ svs/ brownout basic timer 1 1 interrupt vector lcd 160 segments 1,2,3,4 mux f lcd 8 mclk xout jtag interface xin smclk aclk mdb mab emulation p3 port 3 8 i/o 8 module timer_a3 3 cc reg p1 port 1 8 i/o interrupt capability 8 p5 port 5 8 i/o 8 p6 port 6 6 i/o 8 p4 port 4 8 i/o 8 timer_b7 7 cc reg shadow reg usart0 usart1 uart mode spi mode xt2in xt2out oscillator fll+ 8 mhz cpu incl. 16 registers hardware multiplier mpy, mpys mac,macs msp430x44x functional block diagram comparator_ a dv cc1/2 dv ss1/2 av cc av ss rst /nmi p2 flash 60kb 48kb 32kb ram 2kb 1kb watchdog timer wdt 15/16-bit port 2 8 i/o interrupt capability por/ svs/ brownout basic timer 1 1 interrupt vector lcd 160 segments 1,2,3,4 mux f lcd 8 mclk xout jtag interface xin smclk aclk mdb mab emulation p3 port 3 8 i/o 8 module timer_a3 3 cc reg p1 port 1 8 i/o interrupt capability 8 p5 port 5 8 i/o 8 p6 port 6 6 i/o 8 p4 port 4 8 i/o 8 timer_b7 7 cc reg shadow reg usart0 usart1 uart mode spi mode xt2in xt2out adc12 12-bit 8 channels <10 s conv. oscillator fll+ 8 mhz cpu incl. 16 registers hardware multiplier mpy, mpys mac,macs
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 11 post office box 655303 ? dallas, texas 75265 msp430x43x1 terminal functions terminal pn i/o pz i/o description name no. i/o name no. i/o description dv cc1 1 dv cc1 1 digital supply voltage, positive terminal. p6.3 2 i/o p6.3 2 i/o general-purpose digital i/o p6.4 3 i/o p6.4 3 i/o general-purpose digital i/o p6.5 4 i/o p6.5 4 i/o general-purpose digital i/o p6.6 5 i/o p6.6 5 i/o general-purpose digital i/o p6.7/svsin 6 i/o p6.7/svsin 6 i/o general-purpose digital i/o / input to brownout, supply voltage supervisor reserved 7 reserved 7 reserved, do not connect externally xin 8 i xin 8 i input port for crystal oscillator xt1. standard or watch crystals can be connected. xout 9 o xout 9 o output terminal of crystal oscillator xt1 dv ss 10 i dv ss 10 i connect to dv ss dv ss 11 i dv ss 11 i connect to dv ss p5.1/s0 12 i/o p5.1/s0 12 i/o general-purpose digital i/o / lcd segment output 0 p5.0/s1 13 i/o p5.0/s1 13 i/o general-purpose digital i/o / lcd segment output 1 p4.7/s2 14 i/o s2 14 o general-purpose digital i/o / lcd segment output 2 p4.6/s3 15 i/o s3 15 o general-purpose digital i/o / lcd segment output 3 p4.5/s4 16 i/o s4 16 o general-purpose digital i/o / lcd segment output 4 p4.4/s5 17 i/o s5 17 o general-purpose digital i/o / lcd segment output 5 p4.3/s6 18 i/o s6 18 o general-purpose digital i/o / lcd segment output 6 p4.2/s7 19 i/o s7 19 o general-purpose digital i/o / lcd segment output 7 p4.1/s8 20 i/o s8 20 o general-purpose digital i/o / lcd segment output 8 p4.0/s9 21 i/o s9 21 o general-purpose digital i/o / lcd segment output 9 s10 22 o s10 22 o lcd segment output 10 s11 23 o s11 23 o lcd segment output 11 s12 24 o s12 24 o lcd segment output 12 s13 25 o s13 25 o lcd segment output 13 s14 26 o s14 26 o lcd segment output 14 s15 27 o s15 27 o lcd segment output 15 s16 28 o s16 28 o lcd segment output 16 s17 29 o s17 29 o lcd segment output 17 p2.7/s18 30 i/o s18 30 o general-purpose digital i/o / lcd segment output 18 p2.6/caout/s19 31 i/o s19 31 o general-purpose digital i/o / comparator_a output / lcd segment output 19 s20 32 o s20 32 o lcd segment output 20 s21 33 o s21 33 o lcd segment output 21 s22 34 o s22 34 o lcd segment output 22 s23 35 o s23 35 o lcd segment output 23 p3.7/s24 36 i/o s24 36 o general-purpose digital i/o / lcd segment output 24 p3.6/s25 37 i/o s25 37 o general-purpose digital i/o / lcd segment output 25 p3.5/s26 38 i/o s26 38 o general-purpose digital i/o / lcd segment output 26 p3.4/s27 39 i/o s27 39 o general-purpose digital i/o / lcd segment output 27
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 12 post office box 655303 ? dallas, texas 75265 msp430x43x1 terminal functions (continued) terminal pn i/o pz i/o description name no. i/o name no. i/o description p3.3/uclk0/s28 40 i/o s28 40 o general-purpose digital i/o / ext. clock i/p?usart0/uart or spi mode, clock o/p?usart0/spi mode / lcd segment output 28 p3.2/somi0/s29 41 i/o s29 41 o general-purpose digital i/o / slave out/master in of usar t0/spi mode / lcd segment output 29 p3.1/simo0/s30 42 i/o s30 42 o general-purpose digital i/o / slave out/master out of usart0/spi mode / lcd segment output 30 p3.0/ste0/s31 43 i/o s31 43 o general-purpose digital i/o / slave transmit enable-usart0/spi mode / lcd segment output 31 s32 44 o lcd segment output 32 s33 45 o lcd segment output 33 p4.7/s34 46 i/o general-purpose digital i/o / lcd segment output 34 p4.6/s35 47 i/o general-purpose digital i/o / lcd segment output 35 p4.5/s36 48 i/o general-purpose digital i/o / lcd segment output 36 p4.4/s37 49 i/o general-purpose digital i/o / lcd segment output 37 p4.3/s38 50 i/o general-purpose digital i/o / lcd segment output 38 p4.2/s39 51 i/o general-purpose digital i/o / lcd segment output 39 com0 44 o com0 52 o com0?3 are used for lcd backplanes. p5.2/com1 45 i/o p5.2/com1 53 i/o general-purpose digital i/o / common output, com0?3 are used for lcd backplanes. p5.3/com2 46 i/o p5.3/com2 54 i/o general-purpose digital i/o / common output, com0?3 are used for lcd backplanes. p5.4/com3 47 i/o p5.4/com3 55 i/o general-purpose digital i/o / common output, com0?3 are used for lcd backplanes. r03 48 i r03 56 i input port of fourth positive (lowest) analog lcd level (v5) p5.5/r13 49 i/o p5.5/r13 57 i/o general-purpose digital i/o / input port of third most positive analog lcd level (v4 or v3) p5.6/r23 50 i/o p5.6/r23 58 i/o general-purpose digital i/o / input port of second most positive analog lcd level (v2) p5.7/r33 51 i/o p5.7/r33 59 i/o general-purpose digital i/o / output port of most positive analog lcd level (v1) dv cc2 52 dv cc2 60 digital supply voltage, positive terminal. dv ss2 53 dv ss2 61 digital supply voltage, negative terminal. p4.1 62 i/o general-purpose digital i/o p4.0 63 i/o general-purpose digital i/o p3.7 64 i/o general-purpose digital i/o p3.6 65 i/o general-purpose digital i/o p3.5 66 i/o general-purpose digital i/o p3.4 67 i/o general-purpose digital i/o p3.3/uclk0 68 i/o general-purpose digital i/o / external clock input?usart0/uart or spi mode, clock output?usart0/spi mode p3.2/somi0 69 i/o general-purpose digital i/o / slave out/master in of usar t0/spi mode p3.1/simo0 70 i/o general-purpose digital i/o / slave in/master out of usart0/spi mode p3.0/ste0 71 i/o general-purpose digital i/o / slave transmit enable usart0/spi mode p2.7 72 i/o general-purpose digital i/o p2.6/caout 73 i/o general-purpose digital i/o / comparator_a output p2.5/urxd0 54 i/o p2.5/urxd0 74 i/o general-purpose digital i/o / receive data in?usart0/uart mode
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 13 post office box 655303 ? dallas, texas 75265 msp430x43x1 terminal functions (continued) terminal pn i/o pz i/o description name no. i/o name no. i/o description p2.4/utxd0 55 i/o p2.4/utxd0 75 i/o general-purpose digital i/o / transmit data out?usar t0/uart mode p2.3/tb2 56 i/o p2.3/tb2 76 i/o general-purpose digital i/o / timer_b3 ccr2. capture: cci2a/cci2b input, compare: out2 output p2.2/tb1 57 i/o p2.2/tb1 77 i/o general-purpose digital i/o / timer_b3 ccr1. capture: cci1a/cci1b input, compare: out1 output p2.1/tb0 58 i/o p2.1/tb0 78 i/o general-purpose digital i/o / timer_b3 ccr0. capture: cci0a/cci0b input, compare: out0 output p2.0/ta2 59 i/o p2.0/ta2 79 i/o general-purpose digital i/o / timer_a capture: cci2a input, compare: out2 output p1.7/ca1 60 i/o p1.7/ca1 80 i/o general-purpose digital i/o / comparator_a input p1.6/ca0 61 i/o p1.6/ca0 81 i/o general-purpose digital i/o / comparator_a input p1.5/taclk/ aclk 62 i/o p1.5/taclk/ aclk 82 i/o general-purpose digital i/o / timer_a, clock signal taclk input / aclk output (divided by 1, 2, 4, or 8) p1.4/tbclk/ smclk 63 i/o p1.4/tbclk/ smclk 83 i/o general-purpose digital i/o / input clock tbclk?timer_b3 / submain system clock smclk output p1.3/tbouth/ svsout 64 i/o p1.3/tbouth/ svsout 84 i/o general-purpose digital i/o / switch all pwm digital output ports to high impedance?timer_b3 tb0 to tb2 / svs: output of svs comparator p1.2/ta1 65 i/o p1.2/ta1 85 i/o general-purpose digital i/o / timer_a, capture: cci1a input, compare: out1 output p1.1/ta0/mclk 66 i/o p1.1/ta0/mclk 86 i/o general-purpose digital i/o / timer_a. capture: cci0b input / mclk output. note: ta0 is only an input on this pin / bsl receive p1.0/ta0 67 i/o p1.0/ta0 87 i/o general-purpose digital i/o / timer_a. capture: cci0a input, compare: out0 output / bsl transmit xt2out 68 o xt2out 88 o output terminal of crystal oscillator xt2 xt2in 69 i xt2in 89 i input port for crystal oscillator xt2. only standard crystals can be connected. tdo/tdi 70 i/o tdo/tdi 90 i/o test data output port. tdo/tdi data output or programming data input terminal tdi/tclk 71 i tdi/tclk 91 i test data input or test clock input. the device protection fuse is connected to tdi/tclk. tms 72 i tms 92 i test mode select. tms is used as an input port for device programming and test. tck 73 i tck 93 i test clock. tck is the clock input port for device programming and test. rst /nmi 74 i rst /nmi 94 i general-purpose digital i/o / reset input or nonmaskable interrupt input port p6.0 75 i/o p6.0 95 i/o general-purpose digital i/o p6.1 76 i/o p6.1 96 i/o general-purpose digital i/o p6.2 77 i/o p6.2 97 i/o general-purpose digital i/o av ss 78 av ss 98 analog supply voltage, negative terminal. supplies svs, brownout, oscillator, comparator_a, port 1, and lcd resistive divider circuitry. dv ss1 79 dv ss1 99 digital supply voltage, negative terminal. av cc 80 av cc 100 analog supply voltage, positive terminal. supplies svs, brownout, oscillator, comparator_a, port 1, and lcd resistive divider circuitry; must not power up prior to dv cc1 /dv cc2 .
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 14 post office box 655303 ? dallas, texas 75265 msp430x43x terminal functions terminal pn i/o pz i/o description name no. i/o name no. i/o description dv cc1 1 dv cc1 1 digital supply voltage, positive terminal. p6.3/a3 2 i/o p6.3/a3 2 i/o general-purpose digital i/o / analog input a3?12-bit adc p6.4/a4 3 i/o p6.4/a4 3 i/o general-purpose digital i/o / analog input a4?12-bit adc p6.5/a5 4 i/o p6.5/a5 4 i/o general-purpose digital i/o / analog input a5?12-bit adc p6.6/a6 5 i/o p6.6/a6 5 i/o general-purpose digital i/o / analog input a6?12-bit adc p6.7/a7/svsin 6 i/o p6.7/a7/svsin 6 i/o general-purpose digital i/o / analog input a7?12-bit adc, analog / input to brownout, supply voltage supervisor v ref+ 7 o v ref+ 7 o output of positive terminal of the reference voltage in the adc xin 8 i xin 8 i input port for crystal oscillator xt1. standard or watch crystals can be connected. xout 9 o xout 9 o output terminal of crystal oscillator xt1 ve ref+ 10 i ve ref+ 10 i input for an external reference voltage to the adc v ref? /ve ref? 11 i v ref? /ve ref? 11 i negative terminal for the adc? s reference voltage for both sources, the internal reference voltage, or an external applied reference voltage. p5.1/s0 12 i/o p5.1/s0 12 i/o general-purpose digital i/o / lcd segment output 0 p5.0/s1 13 i/o p5.0/s1 13 i/o general-purpose digital i/o / lcd segment output 1 p4.7/s2 14 i/o s2 14 o general-purpose digital i/o / lcd segment output 2 p4.6/s3 15 i/o s3 15 o general-purpose digital i/o / lcd segment output 3 p4.5/s4 16 i/o s4 16 o general-purpose digital i/o / lcd segment output 4 p4.4/s5 17 i/o s5 17 o general-purpose digital i/o / lcd segment output 5 p4.3/s6 18 i/o s6 18 o general-purpose digital i/o / lcd segment output 6 p4.2/s7 19 i/o s7 19 o general-purpose digital i/o / lcd segment output 7 p4.1/s8 20 i/o s8 20 o general-purpose digital i/o / lcd segment output 8 p4.0/s9 21 i/o s9 21 o general-purpose digital i/o / lcd segment output 9 s10 22 o s10 22 o lcd segment output 10 s11 23 o s11 23 o lcd segment output 11 s12 24 o s12 24 o lcd segment output 12 s13 25 o s13 25 o lcd segment output 13 s14 26 o s14 26 o lcd segment output 14 s15 27 o s15 27 o lcd segment output 15 s16 28 o s16 28 o lcd segment output 16 s17 29 o s17 29 o lcd segment output 17 p2.7/adc12clk/ s18 30 i/o s18 30 o general-purpose digital i/o / conversion clock?12-bit adc / lcd segment output 18 p2.6/caout/s19 31 i/o s19 31 o general-purpose digital i/o / comparator_a output / lcd segment output 19 s20 32 o s20 32 o lcd segment output 20 s21 33 o s21 33 o lcd segment output 21 s22 34 o s22 34 o lcd segment output 22 s23 35 o s23 35 o lcd segment output 23 p3.7/s24 36 i/o s24 36 o general-purpose digital i/o / lcd segment output 24 p3.6/s25 37 i/o s25 37 o general-purpose digital i/o / lcd segment output 25 p3.5/s26 38 i/o s26 38 o general-purpose digital i/o / lcd segment output 26 p3.4/s27 39 i/o s27 39 o general-purpose digital i/o / lcd segment output 27
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 15 post office box 655303 ? dallas, texas 75265 msp430x43x terminal functions (continued) terminal pn i/o pz i/o description name no. i/o name no. i/o description p3.3/uclk0/s28 40 i/o s28 40 o general-purpose digital i/o / ext. clock i/p?usart0/uart or spi mode, clock o/p?usart0/spi mode / lcd segment output 28 p3.2/somi0/s29 41 i/o s29 41 o general-purpose digital i/o / slave out/master in of usar t0/spi mode / lcd segment output 29 p3.1/simo0/s30 42 i/o s30 42 o general-purpose digital i/o / slave out/master out of usart0/spi mode / lcd segment output 30 p3.0/ste0/s31 43 i/o s31 43 o general-purpose digital i/o / slave transmit enable-usart0/spi mode / lcd segment output 31 s32 44 o lcd segment output 32 s33 45 o lcd segment output 33 p4.7/s34 46 i/o general-purpose digital i/o / lcd segment output 34 p4.6/s35 47 i/o general-purpose digital i/o / lcd segment output 35 p4.5/s36 48 i/o general-purpose digital i/o / lcd segment output 36 p4.4/s37 49 i/o general-purpose digital i/o / lcd segment output 37 p4.3/s38 50 i/o general-purpose digital i/o / lcd segment output 38 p4.2/s39 51 i/o general-purpose digital i/o / lcd segment output 39 com0 44 o com0 52 o com0?3 are used for lcd backplanes. p5.2/com1 45 i/o p5.2/com1 53 i/o general-purpose digital i/o / common output, com0?3 are used for lcd backplanes. p5.3/com2 46 i/o p5.3/com2 54 i/o general-purpose digital i/o / common output, com0?3 are used for lcd backplanes. p5.4/com3 47 i/o p5.4/com3 55 i/o general-purpose digital i/o / common output, com0?3 are used for lcd backplanes. r03 48 i r03 56 i input port of fourth positive (lowest) analog lcd level (v5) p5.5/r13 49 i/o p5.5/r13 57 i/o general-purpose digital i/o / input port of third most positive analog lcd level (v4 or v3) p5.6/r23 50 i/o p5.6/r23 58 i/o general-purpose digital i/o / input port of second most positive analog lcd level (v2) p5.7/r33 51 i/o p5.7/r33 59 i/o general-purpose digital i/o / output port of most positive analog lcd level (v1) dv cc2 52 dv cc2 60 digital supply voltage, positive terminal. dv ss2 53 dv ss2 61 digital supply voltage, negative terminal. p4.1 62 i/o general-purpose digital i/o p4.0 63 i/o general-purpose digital i/o p3.7 64 i/o general-purpose digital i/o p3.6 65 i/o general-purpose digital i/o p3.5 66 i/o general-purpose digital i/o p3.4 67 i/o general-purpose digital i/o p3.3/uclk0 68 i/o general-purpose digital i/o / external clock input?usart0/uart or spi mode, clock output?usart0/spi mode p3.2/somi0 69 i/o general-purpose digital i/o / slave out/master in of usar t0/spi mode p3.1/simo0 70 i/o general-purpose digital i/o / slave in/master out of usart0/spi mode p3.0/ste0 71 i/o general-purpose digital i/o / slave transmit enable usart0/spi mode p2.7/adc12clk 72 i/o general-purpose digital i/o / conversion clock?12-bit adc p2.6/caout 73 i/o general-purpose digital i/o / comparator_a output p2.5/urxd0 54 i/o p2.5/urxd0 74 i/o general-purpose digital i/o / receive data in?usart0/uart mode
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 16 post office box 655303 ? dallas, texas 75265 msp430x43x terminal functions (continued) terminal pn i/o pz i/o description name no. i/o name no. i/o description p2.4/utxd0 55 i/o p2.4/utxd0 75 i/o general-purpose digital i/o / transmit data out?usar t0/uart mode p2.3/tb2 56 i/o p2.3/tb2 76 i/o general-purpose digital i/o / timer_b3 ccr2. capture: cci2a/cci2b input, compare: out2 output p2.2/tb1 57 i/o p2.2/tb1 77 i/o general-purpose digital i/o / timer_b3 ccr1. capture: cci1a/cci1b input, compare: out1 output p2.1/tb0 58 i/o p2.1/tb0 78 i/o general-purpose digital i/o / timer_b3 ccr0. capture: cci0a/cci0b input, compare: out0 output p2.0/ta2 59 i/o p2.0/ta2 79 i/o general-purpose digital i/o / timer_a capture: cci2a input, compare: out2 output p1.7/ca1 60 i/o p1.7/ca1 80 i/o general-purpose digital i/o / comparator_a input p1.6/ca0 61 i/o p1.6/ca0 81 i/o general-purpose digital i/o / comparator_a input p1.5/taclk/ aclk 62 i/o p1.5/taclk/ aclk 82 i/o general-purpose digital i/o / timer_a, clock signal taclk input / aclk output (divided by 1, 2, 4, or 8) p1.4/tbclk/ smclk 63 i/o p1.4/tbclk/ smclk 83 i/o general-purpose digital i/o / input clock tbclk?timer_b3 / submain system clock smclk output p1.3/tbouth/ svsout 64 i/o p1.3/tbouth/ svsout 84 i/o general-purpose digi tal i/o / switch all pwm digital output ports to high impedance?timer_b3 tb0 to tb2 / svs: output of svs comparator p1.2/ta1 65 i/o p1.2/ta1 85 i/o general-purpose digital i/o / timer_a, capture: cci1a input, compare: out1 output p1.1/ta0/mclk 66 i/o p1.1/ta0/mclk 86 i/o general-purpose digital i/o / timer_a. capture: cci0b input / mclk output. note: ta0 is only an input on this pin / bsl receive p1.0/ta0 67 i/o p1.0/ta0 87 i/o general-purpose digital i/o / timer_a. capture: cci0a input, compare: out0 output / bsl transmit xt2out 68 o xt2out 88 o output terminal of crystal oscillator xt2 xt2in 69 i xt2in 89 i input port for crystal oscillator xt2. only standard crystals can be connected. tdo/tdi 70 i/o tdo/tdi 90 i/o test data output port. tdo/tdi data output or programming data input terminal tdi/tclk 71 i tdi/tclk 91 i test data input or test clock input. the device protection fuse is connected to tdi/tclk. tms 72 i tms 92 i test mode select. tms is used as an input port for device programming and test. tck 73 i tck 93 i test clock. tck is the clock input port for device programming and test. rst /nmi 74 i rst /nmi 94 i general-purpose digital i/o / reset input or nonmaskable interrupt input port p6.0/a0 75 i/o p6.0/a0 95 i/o general-purpose digital i/o / analog input a0 ? 12-bit adc p6.1/a1 76 i/o p6.1/a1 96 i/o general-purpose digital i/o / analog input a1 ? 12-bit adc p6.2/a2 77 i/o p6.2/a2 97 i/o general-purpose digital i/o / analog input a2 ? 12-bit adc av ss 78 av ss 98 analog supply voltage, negative terminal. supplies svs, brownout, oscillator, comparator_a, adc12, port 1, and lcd resistive divider circuitry. dv ss1 79 dv ss1 99 digital supply voltage, negative terminal. av cc 80 av cc 100 analog supply voltage, positive terminal. supplies svs, brownout, oscillator, comparator_a, adc12, port 1, and lcd resistive divider circuitry; must not power up prior to dv cc1 /dv cc2 .
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 17 post office box 655303 ? dallas, texas 75265 msp430x44x1 terminal functions terminal i/o description name no. i/o description dv cc1 1 digital supply voltage, positive terminal. p6.3 2 i/o general-purpose digital i/o p6.4 3 i/o general-purpose digital i/o p6.5 4 i/o general-purpose digital i/o p6.6 5 i/o general-purpose digital i/o p6.7/svsin 6 i/o general-purpose digital i/o / analog input to brownout, supply voltage supervisor reserved 7 o reserved, do not connect externally xin 8 i input port for crystal oscillator xt1. standard or watch crystals can be connected. xout 9 o output terminal of crystal oscillator xt1 dv ss 10 i connect to dv ss dv ss 11 i connect to dv ss p5.1/s0 12 i/o general-purpose digital i/o / lcd segment output 0 p5.0/s1 13 i/o general-purpose digital i/o / lcd segment output 1 s2 14 o lcd segment output 2 s3 15 o lcd segment output 3 s4 16 o lcd segment output 4 s5 17 o lcd segment output 5 s6 18 o lcd segment output 6 s7 19 o lcd segment output 7 s8 20 o lcd segment output 8 s9 21 o lcd segment output 9 s10 22 o lcd segment output 10 s11 23 o lcd segment output 11 s12 24 o lcd segment output 12 s13 25 o lcd segment output 13 s14 26 o lcd segment output 14 s15 27 o lcd segment output 15 s16 28 o lcd segment output 16 s17 29 o lcd segment output 17 s18 30 o lcd segment output 18 s19 31 o lcd segment output 19 s20 32 o lcd segment output 20 s21 33 o lcd segment output 21 s22 34 o lcd segment output 22 s23 35 o lcd segment output 23 s24 36 o lcd segment output 24 s25 37 o lcd segment output 25 s26 38 o lcd segment output 26 s27 39 o lcd segment output 27 s28 40 o lcd segment output 28
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 18 post office box 655303 ? dallas, texas 75265 msp430x44x1 terminal functions (continued) terminal pn i/o description name no. s29 41 o lcd segment output 29 s30 42 o lcd segment output 30 s31 43 o lcd segment output 31 s32 44 o lcd segment output 32 s33 45 o lcd segment output 33 p4.7/s34 46 i/o general-purpose digital i/o / lcd segment output 34 p4.6/s35 47 i/o general-purpose digital i/o / lcd segment output 35 p4.5/uclk1/s36 48 i/o general-purpose digital i/o / external clock input?usart1/uart or spi mode, clock output?usart1/spi mode / lcd segment output 36 p4.4/somi1/s37 49 i/o general-purpose digital i/o / slave out/master in of usart1/spi mode / lcd segment output 37 p4.3/simo1/s38 50 i/o general-purpose digital i/o / slave in/master out of usart1/spi mode / lcd segment output 38 p4.2/ste1/s39 51 i/o general-purpose digital i/o / slave transmit enable?usart1/spi mode / lcd segment output 39 com0 52 o com0?3 are used for lcd backplanes. p5.2/com1 53 i/o general-purpose digital i/o / common output, com0?3 are used for lcd backplanes. p5.3/com2 54 i/o general-purpose digital i/o / common output, com0?3 are used for lcd backplanes. p5.4/com3 55 i/o general-purpose digital i/o / common output, com0?3 are used for lcd backplanes. r03 56 i input port of fourth positive (lowest) analog lcd level (v5) p5.5/r13 57 i/o general-purpose digital i/o / input port of third most positive analog lcd level (v4 or v3) p5.6/r23 58 i/o general-purpose digital i/o / input port of second most positive analog lcd level (v2) p5.7/r33 59 i/o general-purpose digital i/o / output port of most positive analog lcd level (v1) dv cc2 60 digital supply voltage, positive terminal. dv ss2 61 digital supply voltage, negative terminal. p4.1/urxd1 62 i/o general-purpose digital i/o / receive data in?usart1/uart mode p4.0/utxd1 63 i/o general-purpose digital i/o / transmit data out?usart1/uart mode p3.7/tb6 64 i/o general-purpose digital i/o / timer_b7 ccr6 / capture: cci6a/cci6b input, compare: out6 output p3.6/tb5 65 i/o general-purpose digital i/o / timer_b7 ccr5 / capture: cci5a/cci5b input, compare: out5 output p3.5/tb4 66 i/o general-purpose digital i/o / timer_b7 ccr4 / capture: cci4a/cci4b input, compare: out4 output p3.4/tb3 67 i/o general-purpose digital i/o / timer_b7 ccr3 / capture: cci3a/cci3b input, compare: out3 output p3.3/uclk0 68 i/o general-purpose digital i/o / external clock input?usart0/uart or spi mode, clock output?usart0/spi mode p3.2/somi0 69 i/o general-purpose digital i/o / slave out/master in of usart0/spi mode p3.1/simo0 70 i/o general-purpose digital i/o / slave in/master out of usart0/spi mode p3.0/ste0 71 i/o general-purpose digital i/o / slave transmit enable?usart0/spi mode p2.7 72 i/o general-purpose digital i/o p2.6/caout 73 i/o general-purpose digital i/o / comparator_a output p2.5/urxd0 74 i/o general-purpose digital i/o / receive data in?usart0/uart mode p2.4/utxd0 75 i/o general-purpose digital i/o / transmit data out?usart0/uart mode p2.3/tb2 76 i/o general-purpose digital i/o / timer_b7 ccr2. capture: cci2a/cci2b input, compare: out2 output p2.2/tb1 77 i/o general-purpose digital i/o / timer_b7 ccr1. capture: cci1a/cci1b input, compare: out1 output p2.1/tb0 78 i/o general-purpose digital i/o / timer_b7 ccr0. capture: cci0a/cci0b input, compare: out0 output p2.0/ta2 79 i/o general-purpose digital i/o / timer_a capture: cci2a input, compare: out2 output p1.7/ca1 80 i/o general-purpose digital i/o / comparator_a input
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 19 post office box 655303 ? dallas, texas 75265 msp430x44x1 terminal functions (continued) terminal pn i/o description name no. p1.6/ca0 81 i/o general-purpose digital i/o / comparator_a input p1.5/taclk/ aclk 82 i/o general-purpose digital i/o / timer_a, clock signal taclk input / aclk output (divided by 1, 2, 4, or 8) p1.4/tbclk/ smclk 83 i/o general-purpose digital i/o / input clock tbclk?timer_b7 / submain system clock smclk output p1.3/tbouth/ svsout 84 i/o general-purpose digital i/o / switch all pwm digital output ports to high impedance?timer_b7 tb0 to tb6 / svs: output of svs comparator p1.2/ta1 85 i/o general-purpose digital i/o / timer_a, capture: cci1a input, compare: out1 output p1.1/ta0/mclk 86 i/o general-purpose digital i/o / timer_a. capture: cci0b input / mclk output. note: ta0 is only an input on this pin / bsl receive p1.0/ta0 87 i/o general-purpose digital i/o / timer_a. capture: cci0a input, compare: out0 output / bsl transmit xt2out 88 o output terminal of crystal oscillator xt2 xt2in 89 i input port for crystal oscillator xt2. only standard crystals can be connected. tdo/tdi 90 i/o test data output port. tdo/tdi data output or programming data input terminal tdi/tclk 91 i test data input or test clock input. the device protection fuse is connected to tdi/tclk. tms 92 i test mode select. tms is used as an input port for device programming and test. tck 93 i test clock. tck is the clock input port for device programming and test. rst /nmi 94 i reset input or nonmaskable interrupt input port p6.0 95 i/o general-purpose digital i/o p6.1 96 i/o general-purpose digital i/o p6.2 97 i/o general-purpose digital i/o av ss 98 analog supply voltage, negative terminal. supplies svs, brownout, oscillator, comparator_a, port 1, and lcd resistive divider circuitry. dv ss1 99 digital supply voltage, negative terminal. av cc 100 analog supply voltage, positive terminal. supplies svs, brownout, oscillator, comparator_a, port 1, and lcd resistive divider circuitry; must not power up prior to dv cc1 /dv cc2 .
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 20 post office box 655303 ? dallas, texas 75265 msp430x44x terminal functions terminal i/o description name no. i/o description dv cc1 1 digital supply voltage, positive terminal. p6.3/a3 2 i/o general-purpose digital i/o / analog input a3?12-bit adc p6.4/a4 3 i/o general-purpose digital i/o / analog input a4?12-bit adc p6.5/a5 4 i/o general-purpose digital i/o / analog input a5?12-bit adc p6.6/a6 5 i/o general-purpose digital i/o / analog input a6?12-bit adc p6.7/a7/svsin 6 i/o general-purpose digital i/o / analog input a7?12-bit adc / analog input to brownout, supply voltage supervisor v ref+ 7 o output of positive terminal of the reference voltage in the adc xin 8 i input port for crystal oscillator xt1. standard or watch crystals can be connected. xout 9 o output terminal of crystal oscillator xt1 ve ref+ 10 i input for an external reference voltage to the adc v ref? /ve ref? 11 i negative terminal for the adc?s reference voltage for both sources, the internal reference voltage, or an external applied reference voltage p5.1/s0 12 i/o general-purpose digital i/o / lcd segment output 0 p5.0/s1 13 i/o general-purpose digital i/o / lcd segment output 1 s2 14 o lcd segment output 2 s3 15 o lcd segment output 3 s4 16 o lcd segment output 4 s5 17 o lcd segment output 5 s6 18 o lcd segment output 6 s7 19 o lcd segment output 7 s8 20 o lcd segment output 8 s9 21 o lcd segment output 9 s10 22 o lcd segment output 10 s11 23 o lcd segment output 11 s12 24 o lcd segment output 12 s13 25 o lcd segment output 13 s14 26 o lcd segment output 14 s15 27 o lcd segment output 15 s16 28 o lcd segment output 16 s17 29 o lcd segment output 17 s18 30 o lcd segment output 18 s19 31 o lcd segment output 19 s20 32 o lcd segment output 20 s21 33 o lcd segment output 21 s22 34 o lcd segment output 22 s23 35 o lcd segment output 23 s24 36 o lcd segment output 24 s25 37 o lcd segment output 25 s26 38 o lcd segment output 26 s27 39 o lcd segment output 27 s28 40 o lcd segment output 28
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 21 post office box 655303 ? dallas, texas 75265 msp430x44x terminal functions (continued) terminal pn i/o description name no. s29 41 o lcd segment output 29 s30 42 o lcd segment output 30 s31 43 o lcd segment output 31 s32 44 o lcd segment output 32 s33 45 o lcd segment output 33 p4.7/s34 46 i/o general-purpose digital i/o / lcd segment output 34 p4.6/s35 47 i/o general-purpose digital i/o / lcd segment output 35 p4.5/uclk1/s36 48 i/o general-purpose digital i/o / external clock input?usart1/uart or spi mode, clock output?usart1/spi mode / lcd segment output 36 p4.4/somi1/s37 49 i/o general-purpose digital i/o / slave out/master in of usart1/spi mode / lcd segment output 37 p4.3/simo1/s38 50 i/o general-purpose digital i/o / slave in/master out of usart1/spi mode / lcd segment output 38 p4.2/ste1/s39 51 i/o general-purpose digital i/o / slave transmit enable?usart1/spi mode / lcd segment output 39 com0 52 o com0?3 are used for lcd backplanes. p5.2/com1 53 i/o general-purpose digital i/o / common output, com0?3 are used for lcd backplanes. p5.3/com2 54 i/o general-purpose digital i/o / common output, com0?3 are used for lcd backplanes. p5.4/com3 55 i/o general-purpose digital i/o / common output, com0?3 are used for lcd backplanes. r03 56 i input port of fourth positive (lowest) analog lcd level (v5) p5.5/r13 57 i/o general-purpose digital i/o / input port of third most positive analog lcd level (v4 or v3) p5.6/r23 58 i/o general-purpose digital i/o / input port of second most positive analog lcd level (v2) p5.7/r33 59 i/o general-purpose digital i/o / output port of most positive analog lcd level (v1) dv cc2 60 digital supply voltage, positive terminal. dv ss2 61 digital supply voltage, negative terminal. p4.1/urxd1 62 i/o general-purpose digital i/o / receive data in?usart1/uart mode p4.0/utxd1 63 i/o general-purpose digital i/o / transmit data out?usart1/uart mode p3.7/tb6 64 i/o general-purpose digital i/o / timer_b7 ccr6 / capture: cci6a/cci6b input, compare: out6 output p3.6/tb5 65 i/o general-purpose digital i/o / timer_b7 ccr5 / capture: cci5a/cci5b input, compare: out5 output p3.5/tb4 66 i/o general-purpose digital i/o / timer_b7 ccr4 / capture: cci4a/cci4b input, compare: out4 output p3.4/tb3 67 i/o general-purpose digital i/o / timer_b7 ccr3 / capture: cci3a/cci3b input, compare: out3 output p3.3/uclk0 68 i/o general-purpose digital i/o / external clock input?usart0/uart or spi mode, clock output?usart0/spi mode p3.2/somi0 69 i/o general-purpose digital i/o / slave out/master in of usart0/spi mode p3.1/simo0 70 i/o general-purpose digital i/o / slave in/master out of usart0/spi mode p3.0/ste0 71 i/o general-purpose digital i/o / slave transmit enable?usart0/spi mode p2.7/adc12clk 72 i/o general-purpose digital i/o / conversion clock?12-bit adc p2.6/caout 73 i/o general-purpose digital i/o / comparator_a output p2.5/urxd0 74 i/o general-purpose digital i/o / receive data in?usart0/uart mode p2.4/utxd0 75 i/o general-purpose digital i/o / transmit data out?usart0/uart mode p2.3/tb2 76 i/o general-purpose digital i/o / timer_b7 ccr2. capture: cci2a/cci2b input, compare: out2 output p2.2/tb1 77 i/o general-purpose digital i/o / timer_b7 ccr1. capture: cci1a/cci1b input, compare: out1 output p2.1/tb0 78 i/o general-purpose digital i/o / timer_b7 ccr0. capture: cci0a/cci0b input, compare: out0 output p2.0/ta2 79 i/o general-purpose digital i/o / timer_a capture: cci2a input, compare: out2 output p1.7/ca1 80 i/o general-purpose digital i/o / comparator_a input
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 22 post office box 655303 ? dallas, texas 75265 msp430x44x terminal functions (continued) terminal pn i/o description name no. p1.6/ca0 81 i/o general-purpose digital i/o / comparator_a input p1.5/taclk/ aclk 82 i/o general-purpose digital i/o / timer_a, clock signal taclk input / aclk output (divided by 1, 2, 4, or 8) p1.4/tbclk/ smclk 83 i/o general-purpose digital i/o / input clock tbclk?timer_b7 / submain system clock smclk output p1.3/tbouth/ svsout 84 i/o general-purpose digital i/o / switch all pwm digital output ports to high impedance?timer_b7 tb0 to tb6 / svs: output of svs comparator p1.2/ta1 85 i/o general-purpose digital i/o / timer_a, capture: cci1a input, compare: out1 output p1.1/ta0/mclk 86 i/o general-purpose digital i/o / timer_a. capture: cci0b input / mclk output. note: ta0 is only an input on this pin / bsl receive p1.0/ta0 87 i/o general-purpose digital i/o / timer_a. capture: cci0a input, compare: out0 output / bsl transmit xt2out 88 o output terminal of crystal oscillator xt2 xt2in 89 i input port for crystal oscillator xt2. only standard crystals can be connected. tdo/tdi 90 i/o test data output port. tdo/tdi data output or programming data input terminal tdi/tclk 91 i test data input or test clock input. the device protection fuse is connected to tdi/tclk. tms 92 i test mode select. tms is used as an input port for device programming and test. tck 93 i test clock. tck is the clock input port for device programming and test. rst /nmi 94 i reset input or nonmaskable interrupt input port p6.0/a0 95 i/o general-purpose digital i/o, analog input a0?12-bit adc p6.1/a1 96 i/o general-purpose digital i/o, analog input a1?12-bit adc p6.2/a2 97 i/o general-purpose digital i/o, analog input a2?12-bit adc av ss 98 analog supply voltage, negative terminal. supplies svs, brownout, oscillator, comparator_a, adc12, port 1, and lcd resistive divider circuitry. dv ss1 99 digital supply voltage, negative terminal. av cc 100 analog supply voltage, positive terminal. supplies svs, brownout, oscillator, comparator_a, adc12, port 1, and lcd resistive divider circuitry; must not power up prior to dv cc1 /dv cc2 .
general-purpose register program counter stack pointer status register constant generator general-purpose register general-purpose register general-purpose register pc/r0 sp/r1 sr/cg1/r2 cg2/r3 r4 r5 r12 r13 general-purpose register general-purpose register r6 r7 general-purpose register general-purpose register r8 r9 general-purpose register general-purpose register r10 r11 general-purpose register general-purpose register r14 r15 msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 23 post office box 655303 ? dallas, texas 75265 short-form description cpu the msp430 cpu has a 16-bit risc architecture that is highly transparent to the application. all operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. the cpu is integrated with 16 registers that provide reduced instruction execution time. the register-to-register operation execution time is one cycle of the cpu clock. four of the registers, r0 to r3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. the remaining registers are general-purpose registers. peripherals are connected to the cpu using data, address, and control buses, and can be handled with all instructions. instruction set the instruction set consists of 51 instructions with three formats and seven address modes. each instruction can operate on word and byte data. table 1 shows examples of the three types of instruction formats; table 2 shows the address modes. table 1. instruction word formats dual operands, source-destination e.g. add r4,r5 r4 + r5 ???> r5 single operands, destination only e.g. call r8 pc ??>(tos), r8??> pc relative jump, un/conditional e.g. jne jump-on-equal bit = 0 table 2. address mode descriptions address mode s d syntax example operation register mov rs,rd mov r10,r11 r10 ??> r11 indexed mov x(rn),y(rm) mov 2(r5),6(r6) m(2+r5)??> m(6+r6) symbolic (pc relative) mov ede,toni m(ede) ??> m(toni) absolute mov &mem,&tcdat m(mem) ??> m(tcdat) indirect mov @rn,y(rm) mov @r10,tab(r6) m(r10) ??> m(tab+r6) indirect autoincrement mov @rn+,rm mov @r10+,r11 m(r10) ??> r11 r10 + 2??> r10 immediate mov #x,toni mov #45,toni #45 ??> m(toni) note: s = source d = destination
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 24 post office box 655303 ? dallas, texas 75265 operating modes the msp430 has one active mode and five software selectable low-power modes of operation. an interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program. the following six operating modes can be configured by software: active mode (am) ? all clocks are active low-power mode 0 (lpm0) ? cpu is disabled ? aclk and smclk remain active, mclk is disabled ? fll+ loop control remains active low-power mode 1 (lpm1) ? cpu is disabled ? fll+ loop control is disabled ? aclk and smclk remain active, mclk is disabled low-power mode 2 (lpm2) ? cpu is disabled ? mclk, fll+ loop control, and dcoclk are disabled ? dco?s dc generator remains enabled ? aclk remains active low-power mode 3 (lpm3) ? cpu is disabled ? mclk, fll+ loop control, and dcoclk are disabled ? dco?s dc generator is disabled ? aclk remains active low-power mode 4 (lpm4) ? cpu is disabled ? aclk is disabled ? mclk, fll+ loop control, and dcoclk are disabled ? dco?s dc generator is disabled ? crystal oscillator is stopped
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 25 post office box 655303 ? dallas, texas 75265 interrupt vector addresses the interrupt vectors and the power-up starting address are located in the address range 0ffffh to 0ffe0h. the vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. table 3. interrupt sources, flags, and vectors interrupt source interrupt flag system interrupt word address priority power-up external reset watchdog flash memory wdtifg keyv (see note 1) reset 0fffeh 15, highest nmi oscillator fault flash memory access violation nmiifg (see notes 1 and 3) ofifg (see notes 1 and 3) accvifg (see notes 1 and 3) (non)maskable (non)maskable (non)maskable 0fffch 14 timer_b7 ? tbccr0 ccifg (see note 2) maskable 0fffah 13 timer_b7 ? tbccr1 to tbccr6 ccifgs tbifg (see notes 1 and 2) maskable 0fff8h 12 comparator_a caifg maskable 0fff6h 11 watchdog timer wdtifg maskable 0fff4h 10 usart0 receive urxifg0 maskable 0fff2h 9 usart0 transmit utxifg0 maskable 0fff0h 8 adc12 (see note 4) adc12ifg (see notes 1 and 2) maskable 0ffeeh 7 timer_a3 taccr0 ccifg (see note 2) maskable 0ffech 6 timer_a3 taccr1 and taccr2 ccifgs, taifg (see notes 1 and 2) maskable 0ffeah 5 i/o port p1 (eight flags) p1ifg.0 to p1ifg.7 (see notes 1 and 2) maskable 0ffe8h 4 usart1 receive ? urxifg1 maskable 0ffe6h 3 usart1 transmit ? utxifg1 maskable 0ffe4h 2 i/o port p2 (eight flags) p2ifg.0 to p2ifg.7 (see notes 1 and 2) maskable 0ffe2h 1 basic timer1 btifg maskable 0ffe0h 0, lowest ? ?43x(1) uses timer_b3 with tbccr0, 1 and 2 ccifg flags, and tbifg. ?44x(1) uses timer_b7 with tbccr0 ccifg, tbccr1 to tbccr6 ccifgs, and tbifg ? usart1 is implemented in ?44x(1) only. notes: 1. multiple source flags 2. interrupt flags are located in the module. 3. (non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not d isable it. 4. adc12 is not implemented in msp430x43x1 and msp430x44x1 devices.
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 26 post office box 655303 ? dallas, texas 75265 special function registers most interrupt and module-enable bits are collected in the lowest address space. special-function register bits not allocated to a functional purpose are not physically present in the device. this arrangement provides simple software access. interrupt enable 1 and 2 7654 0 utxie0 ofie wdtie 32 1 rw?0 rw?0 rw?0 address 0h urxie0 accvie nmiie rw?0 rw?0 rw?0 wdtie: watchdog-timer interrupt enable. inactive if watchdog mode is selected. active if watchdog timer is configured in interval timer mode. ofie: oscillator-fault-interrupt enable nmiie: nonmaskable-interrupt enable accvie: flash access violation interrupt enable urxie0: usart0: uart and spi receive-interrupt enable utxie0: usart0: uart and spi transmit-interrupt enable 7654 0 utxie1 32 1 rw?0 rw?0 address 01h urxie1 rw?0 btie urxie1: usart1: uart and spi receive-interrupt enable (msp430f44x(1) devices only) utxie1: usart1: uart and spi transmit-interrupt enable (msp430f44x(1) devices only) btie: basic timer interrupt enable interrupt flag register 1 and 2 7654 0 utxifg0 ofifg wdtifg 32 1 rw?0 rw?1 rw?(0) address 02h urxifg0 nmiifg rw?1 rw?0 wdtifg: set on watchdog timer overflow (in watchdog mode) or security key violation. reset on v cc power up or a reset condition at the rst /nmi pin in reset mode. ofifg: flag set on oscillator fault nmiifg: set via rst /nmi pin urxifg0: usart0: uart and spi receive flag utxifg0: usart0: uart and spi transmit flag 7654 0 utxifg1 32 1 rw?1 rw?0 address 03h urxifg1 btifg rw urxifg1: usart1: uart and spi receive flag (msp430f44x(1) devices only) utxifg1: usart1: uart and spi transmit flag (msp430f44x(1) devices only) btifg: basic timer flag
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 27 post office box 655303 ? dallas, texas 75265 module enable registers 1 and 2 7654 0 utxe0 32 1 rw?0 rw?0 address 04h urxe0 uspie0 urxe0: usart0: uart mode receive enable utxe0: usart0: uart mode transmit enable uspie0: usart0: spi mode transmit and receive enable 7654 0 utxe1 32 1 rw?0 rw?0 address 05h urxe1 uspie1 urxe1: usart1: uart mode receive enable (msp430f44x(1) devices only) utxe1: usart1: uart mode transmit enable (msp430f44x(1) devices only) uspie1: usart1: spi mode transmit and receive enable (msp430f44x(1) devices only) rw?0,1: legend: rw: bit can be read and written bit can be read and written. it is reset or set by puc. bit can be read and written. it is reset or set by por. sfr bit not present in device rw?(0,1): memory organization msp430f435 msp430f4351 msp430f436 msp430f4361 msp430f437 msp430f4371 msp430f447 msp430f448 msp430f4481 msp430f449 msp430f4491 memory main: interrupt vector main: code memory size flash flash 16kb 0ffffh ? 0ffe0h 0ffffh ? 0c000h 24kb 0ffffh ? 0ffe0h 0ffffh ? 0a000h 32kb 0ffffh ? 0ffe0h 0ffffh ? 08000h 48kb 0ffffh ? 0ffe0h 0ffffh ? 04000h 60kb 0ffffh ? 0ffe0h 0ffffh ? 01100h information memory size flash 256 byte 010ffh ? 01000h 256 byte 010ffh ? 01000h 256 byte 010ffh ? 01000h 256 byte 010ffh ? 01000h 256 byte 010ffh ? 01000h boot memory size rom 1kb 0fffh ? 0c00h 1kb 0fffh ? 0c00h 1kb 0fffh ? 0c00h 1kb 0fffh ? 0c00h 1kb 0fffh ? 0c00h ram size 512 byte 03ffh ? 0200h 1kb 05ffh ? 0200h 1kb 05ffh ? 0200h 2kb 09ffh ? 0200h 2kb 09ffh ? 0200h peripherals 16-bit 8-bit 8-bit sfr 01ffh ? 0100h 0ffh ? 010h 0fh ? 00h 01ffh ? 0100h 0ffh ? 010h 0fh ? 00h 01ffh ? 0100h 0ffh ? 010h 0fh ? 00h 01ffh ? 0100h 0ffh ? 010h 0fh ? 00h 01ffh ? 0100h 0ffh ? 010h 0fh ? 00h bootstrap loader (bsl) the msp430 bootstrap loader (bsl) enables users to program the flash memory or ram using a uart serial interface. access to the msp430 memory via the bsl is protected by user-defined password. for complete description of the features of the bsl and its implementation, see the msp430 memory programming user?s guide, literature number slau265. bsl function pn package pins pz package pins data transmit 67 - p1.0 87 - p1.0 data receive 66 - p1.1 86 - p1.1
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 28 post office box 655303 ? dallas, texas 75265 flash memory the flash memory can be programmed via the jtag port, the bootstrap loader, or in-system by the cpu. the cpu can perform single-byte and single-word writes to the flash memory. features of the flash memory include: flash memory has n segments of main memory and two segments of information memory (a and b) of 128 bytes each. each segment in main memory is 512 bytes in size. segments 0 to n may be erased in one step, or each segment may be individually erased. segments a and b can be erased individually, or as a group with segments 0 to n. segments a and b are also called information memory. new devices may have some bytes programmed in the information memory (needed for test during manufacturing). the user should perform an erase of the information memory prior to the first use. segment 0 w/ interrupt vectors segment 1 segment 2 segment n-1 segment n segment a segment b main memory information memory 24kb 0ffffh 0fe00h 0fdffh 0fc00h 0fbffh 0fa00h 0f9ffh 16kb 0ffffh 0fe00h 0fdffh 0fc00h 0fbffh 0fa00h 0f9ffh 32kb 0ffffh 0fe00h 0fdffh 0fc00h 0fbffh 0fa00h 0f9ffh 48kb 0ffffh 0fe00h 0fdffh 0fc00h 0fbffh 0fa00h 0f9ffh 60kb 0ffffh 0fe00h 0fdffh 0fc00h 0fbffh 0fa00h 0f9ffh 0a400h 0a3ffh 0a200h 0a1ffh 0a000h 010ffh 01080h 0107fh 01000h 0c400h 0c3ffh 0c200h 0c1ffh 0c000h 010ffh 01080h 0107fh 01000h 08400h 083ffh 08200h 081ffh 08000h 010ffh 01080h 0107fh 01000h 04400h 043ffh 04200h 041ffh 04000h 010ffh 01080h 0107fh 01000h 01400h 013ffh 01200h 011ffh 01100h 010ffh 01080h 0107fh 01000h
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 29 post office box 655303 ? dallas, texas 75265 peripherals peripherals are connected to the cpu through data, address, and control buses and can be handled using all instructions. for compl ete module descriptions, see the msp430x4xx family user?s guide , literature number slau056. digital i/o there are six 8-bit i/o ports implemented?ports p1 through p6: all individual i/o bits are independently programmable. any combination of input, output, and interrupt conditions is possible. edge-selectable interrupt input capability for all the eight bits of ports p1 and p2. read/write access to port-control registers is supported by all instructions. oscillator and system clock the clock system in the msp430x43x(1) and msp43x44x(1) family of devices is supported by the fll+ module, which includes support for a 32768-hz watch crystal oscillator, an internal digitally controlled oscillator (dco), and a high-frequency crystal oscillator. the fll+ clock module is designed to meet the requirements of both low system cost and low power consumption. the fll+ features a digital frequency-locked loop (fll) hardware that, in conjunction with a digital modulator, stabilizes the dco frequency to a programmable multiple of the watch crystal frequency. the internal dco provides a fast turn-on clock source and stabilizes in less than 6 s. the fll+ module provides the following clock signals: auxiliary clock (aclk), sourced from a 32768-hz watch crystal or a high-frequency crystal main clock (mclk), the system clock used by the cpu sub-main clock (smclk), the sub-system clock used by the peripheral modules aclk/n, the buffered output of aclk, aclk/2, aclk/4, or aclk/8 brownout, supply voltage supervisor (svs) the brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. the supply voltage supervisor (svs) circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (svm, the device is not automatically reset). the cpu begins code execution after the brownout circuit releases the device reset. however, v cc may not have ramped to v cc(min) at that time. the user must insure the default fll+ settings are not changed until v cc reaches v cc(min) . if desired, the svs circuit can be used to determine when v cc reaches v cc(min) . hardware multiplier (msp430x44x(1) only) the multiplication operation is supported by a dedicated peripheral module. the module performs 16 16, 16 8, 8 16, and 8 8 bit operations. the module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations. the result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. no additional clock cycles are required. watchdog timer (wdt) the primary function of the watchdog timer (wdt) module is to perform a controlled system restart after a software problem occurs. if the selected time interval expires, a system reset is generated. if the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 30 post office box 655303 ? dallas, texas 75265 usart0 the msp430x43x(1) and the msp430x44x(1) have one hardware universal synchronous/asynchronous receive transmit (usart0) peripheral module that is used for serial data communication. the usart supports synchronous spi (3 or 4 pin) and asynchronous uart communication protocols, using double-buffered transmit and receive channels. usart1 (msp430x44x(1) only) the msp430x44x(1) has a second hardware universal synchronous/asynchronous receive transmit (usart1) peripheral module that is used for serial data communication. the usart supports synchronous spi (3 or 4 pin) and asynchronous uart communicati on protocols, using double-buffered transmit and receive channels. operation of usart1 is identical to usart0. timer_a3 timer_a3 is a 16-bit timer/counter with three capture/compare registers. timer_a3 can support multiple capture/compares, pwm outputs, and interval timing. timer_a3 also has extensive interrupt capabilities. interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. timer_a3 signal connections input pin number device input module input module module output output pin number pn pz device input signal module input name module block output signal pn pz 62 - p1.5 82 - p1.5 taclk taclk aclk aclk timer na smclk smclk timer na 62 - p1.5 82 - p1.5 taclk inclk 67 - p1.0 87 - p1.0 ta0 cci0a 67 - p1.0 87 - p1.0 66 - p1.1 86 - p1.1 ta0 cci0b ccr0 ta0 dv ss gnd ccr0 ta0 dv cc v cc 65 - p1.2 85 - p1.2 ta1 cci1a 14 - p1.2 85 - p1.2 caout (internal) cci1b ccr1 ta1 adc12 (internal) ? dv ss gnd ccr1 ta1 dv cc v cc 59 - p2.0 79 - p2.0 ta2 cci2a 15 - p1.3 79 - p2.0 aclk (internal) cci2b ccr2 ta2 dv ss gnd ccr2 ta2 dv cc v cc ? not implemented in msp430x43x1 and msp430x44x1 devices. timer_b3 (msp430x43x(1) only) timer_b3 is a 16-bit timer/counter with three capture/compare registers. timer_b3 can support multiple capture/compares, pwm outputs, and interval timing. timer_b3 also has extensive interrupt capabilities. interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g january 2002 revised october 2009 31 post office box 655303 ? dallas, texas 75265 timer_b7 (msp430x44x(1) only) timer_b7 is a 16-bit timer/counter with seven capture/compare registers. timer_b7 can support multiple capture/compares, pwm outputs, and interval timing. timer_b7 also has extensive interrupt capabilities. interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. timer_b3/b7 signal connections ? input pin number device input module input module module output output pin number pn pz device input signal module input name module block output signal pn pz 63 - p1.4 83 - p1.4 tbclk tbclk aclk aclk timer na smclk smclk timer na 63 - p1.4 83 - p1.4 tbclk inclk 58 - p2.1 78 - p2.1 tb0 cci0a 58 - p2.1 78 - p2.1 58 - p2.1 78 - p2.1 tb0 cci0b ccr0 ? tb0 adc12 (internal) ? dv ss gnd ccr0 ? tb0 dv cc v cc 57 - p2.2 77 - p2.2 tb1 cci1a 57 - p2.2 77 - p2.2 57 - p2.2 77 - p2.2 tb1 cci1b ccr1 ? tb1 adc12 (internal) ? dv ss gnd ccr1 ? tb1 dv cc v cc 56 - p2.3 76 - p2.3 tb2 cci2a 56 - p2.3 76 - p2.3 56 - p2.3 76 - p2.3 tb2 cci2b ccr2 ? tb2 dv ss gnd ccr2 ? tb2 dv cc v cc 67 - p3.4 tb3 cci3a 67 - p3.4 67 - p3.4 tb3 cci3b ccr3 tb3 dv ss gnd ccr3 tb3 dv cc v cc 66 - p3.5 tb4 cci4a 66 - p3.5 66 - p3.5 tb4 cci4b ccr4 tb4 dv ss gnd ccr4 tb4 dv cc v cc 65 - p3.6 tb5 cci5a 65 - p3.6 65 - p3.6 tb5 cci5b ccr5 tb5 dv ss gnd ccr5 tb5 dv cc v cc 64 - p3.7 tb6 cci6a 64 - p3.7 aclk (internal) cci6b ccr6 tb6 dv ss gnd ccr6 tb6 dv cc v cc ? timer_b3 implements three capture/compare blocks (ccr0, ccr1 and ccr2 only). ? not implemented in msp430x43x1 and msp430x44x1 devices.
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 32 post office box 655303 ? dallas, texas 75265 comparator_a the primary function of the comparator_a module is to support precision slope analog-to-digital conversions, battery-voltage supervision, and monitoring of external analog signals. adc12 (not implemented in msp430x43x1 and msp430x44x1) the adc12 module supports fast, 12-bit analog-to-digital conversions. the module implements a 12-bit sar core, sample select control, reference generator and a 16 word conversion-and-control buffer. the conversion-and-control buffer allows up to 16 independent adc samples to be converted and stored without any cpu intervention. basic timer1 the basic t imer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. both timers can be read and written by software. the basic timer1 can be used to generate periodic interrupts and clock for the lcd module. lcd driver the lcd driver generates the segment and common signals required to drive an lcd display. the lcd controller has dedicated data memory to hold segment drive information. common and segment signals are generated as defined by the mode. static, 2-mux, 3-mux, and 4-mux lcds are supported by this peripheral.
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 33 post office box 655303 ? dallas, texas 75265 peripheral file map peripherals with word access watchdog watchdog timer control wdtctl 0120h timer_b7/ capture/compare register 6 tbccr6 019eh _ timer_b3 (see note 1) capture/compare register 5 tbccr5 019ch (see note 1) capture/compare register 4 tbccr4 019ah capture/compare register 3 tbccr3 0198h capture/compare register 2 tbccr2 0196h capture/compare register 1 tbccr1 0194h capture/compare register 0 tbccr0 0192h timer_b register tbr 0190h capture/compare control 6 tbcctl6 018eh capture/compare control 5 tbcctl5 018ch capture/compare control 4 tbcctl4 018ah capture/compare control 3 tbcctl3 0188h capture/compare control 2 tbcctl2 0186h capture/compare control 1 tbcctl1 0184h capture/compare control 0 tbcctl0 0182h timer_b control tbctl 0180h timer_b interrupt vector tbiv 011eh timer_a3 reserved 017eh _ reserved 017ch reserved 017ah reserved 0178h capture/compare register 2 taccr2 0176h capture/compare register 1 taccr1 0174h capture/compare register 0 taccr0 0172h timer_a register tar 0170h reserved 016eh reserved 016ch reserved 016ah reserved 0168h capture/compare control 2 tacctl2 0166h capture/compare control 1 tacctl1 0164h capture/compare control 0 tacctl0 0162h timer_a control tactl 0160h timer_a interrupt vector taiv 012eh hardware sum extend sumext 013eh multiplier (msp430x44x(1) result high word reshi 013ch (msp430x44x(1) onl y) result low word reslo 013ah only) second operand op2 0138h multiply signed + accumulate/operand1 macs 0136h multiply + accumulate/operand1 mac 0134h multiply signed/operand1 mpys 0132h multiply unsigned/operand1 mpy 0130h note 1: timer_b7 in the msp430x44x(1) family has seven ccrs; timer_b3 in the msp430x43x(1) family has three ccrs.
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 34 post office box 655303 ? dallas, texas 75265 peripheral file map (continued) peripherals with word access (continued) flash flash control 3 fctl3 012ch flash control 2 fctl2 012ah flash control 1 fctl1 0128h adc12 conversion memory 15 adc12mem15 015eh (not implemented in msp430f43x1 and conversion memory 14 adc12mem14 015ch msp430f43x1 and msp430f44x1 ) conversion memory 13 adc12mem13 015ah msp430f44x1) conversion memory 12 adc12mem12 0158h conversion memory 11 adc12mem11 0156h conversion memory 10 adc12mem10 0154h conversion memory 9 adc12mem9 0152h conversion memory 8 adc12mem8 0150h conversion memory 7 adc12mem7 014eh conversion memory 6 adc12mem6 014ch conversion memory 5 adc12mem5 014ah conversion memory 4 adc12mem4 0148h conversion memory 3 adc12mem3 0146h conversion memory 2 adc12mem2 0144h conversion memory 1 adc12mem1 0142h conversion memory 0 adc12mem0 0140h interrupt-vector-word register adc12iv 01a8h inerrupt-enable register adc12ie 01a6h inerrupt-flag register adc12ifg 01a4h control register 1 adc12ctl1 01a2h control register 0 adc12ctl0 01a0h adc memory-control register15 adc12mctl15 08fh adc memory-control register14 adc12mctl14 08eh adc memory-control register13 adc12mctl13 08dh adc memory-control register12 adc12mctl12 08ch adc memory-control register11 adc12mctl11 08bh adc memory-control register10 adc12mctl10 08ah adc memory-control register9 adc12mctl9 089h adc memory-control register8 adc12mctl8 088h adc memory-control register7 adc12mctl7 087h adc memory-control register6 adc12mctl6 086h adc memory-control register5 adc12mctl5 085h adc memory-control register4 adc12mctl4 084h adc memory-control register3 adc12mctl3 083h adc memory-control register2 adc12mctl2 082h adc memory-control register1 adc12mctl1 081h adc memory-control register0 adc12mctl0 080h
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 35 post office box 655303 ? dallas, texas 75265 peripheral file map (continued) peripherals with byte access lcd lcd memory 20 : lcd memory 16 lcd memory 15 : lcd memory 1 lcd control and mode lcdm20 : lcdm16 lcdm15 : lcdm1 lcdctl 0a4h : 0a0h 09fh : 091h 090h usart1 transmit buffer u1txbuf 07fh (msp430f44x(1) only) receive buffer u1rxbuf 07eh only) baud rate u1br1 07dh baud rate u1br0 07ch modulation control u1mctl 07bh receive control u1rctl 07ah transmit control u1tctl 079h usart control u1ctl 078h usart0 transmit buffer u0txbuf 077h receive buffer u0rxbuf 076h baud rate u0br1 075h baud rate u0br0 074h modulation control u0mctl 073h receive control u0rctl 072h transmit control u0tctl 071h usart control u0ctl 070h comparator_a comparator_a port disable capd 05bh p _ comparator_a control2 cactl2 05ah comparator_a control1 cactl1 059h brownout, svs svs control register (reset by brownout signal) svsctl 056h fll+ clock fll+ control1 fll_ctl1 054h fll+ control0 fll_ctl0 053h system clock frequency control scfqctl 052h system clock frequency integrator scfi1 051h system clock frequency integrator scfi0 050h basic timer1 bt counter2 bt counter1 bt control btcnt2 btcnt1 btctl 047h 046h 040h port p6 port p6 selection p6sel 037h port p6 direction p6dir 036h port p6 output p6out 035h port p6 input p6in 034h port p5 port p5 selection p5sel 033h port p5 direction p5dir 032h port p5 output p5out 031h port p5 input p5in 030h
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 36 post office box 655303 ? dallas, texas 75265 peripheral file map (continued) peripherals with byte access (continued) port p4 port p4 selection p4sel 01fh port p4 direction p4dir 01eh port p4 output p4out 01dh port p4 input p4in 01ch port p3 port p3 selection p3sel 01bh port p3 direction p3dir 01ah port p3 output p3out 019h port p3 input p3in 018h port p2 port p2 selection p2sel 02eh port p2 interrupt enable p2ie 02dh port p2 interrupt-edge select p2ies 02ch port p2 interrupt flag p2ifg 02bh port p2 direction p2dir 02ah port p2 output p2out 029h port p2 input p2in 028h port p1 port p1 selection p1sel 026h port p1 interrupt enable p1ie 025h port p1 interrupt-edge select p1ies 024h port p1 interrupt flag p1ifg 023h port p1 direction p1dir 022h port p1 output p1out 021h port p1 input p1in 020h special functions sfr module enable2 me2 005h p sfr module enable1 me1 004h sfr interrupt flag2 ifg2 003h sfr interrupt flag1 ifg1 002h sfr interrupt enable2 ie2 001h sfr interrupt enable1 ie1 000h absolute maximum ratings over operating free-air temperature (unless otherwise noted) ? voltage applied at v cc to v ss ?0.3 v to 4.1 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage applied to any pin (see note) ?0.3 v to v cc + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . diode current at any device terminal . 2 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature, t stg : unprogrammed device ?55 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . programmed device ?55 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditi ons? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note: all voltages referenced to v ss . the jtag fuse-blow voltage, v fb , is allowed to exceed the absolute maximum rating. the voltage is applied to the tdi/tclk pin when blowing the jtag fuse.
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 37 post office box 655303 ? dallas, texas 75265 recommended operating conditions min nom max unit supply voltage during program execution v cc (av cc = dv cc1 = dv cc2 = v cc ) (see note 1) msp430f43x(1), msp430f44x(1) 1.8 3.6 v supply voltage during program execution, svs enabled, poron=1 (see note 1 and note 2) v cc (av cc = dv cc1 = dv cc2 = v cc ) msp430f43x(1), msp430f44x(1) 2 3.6 v supply voltage during flash memory programming v cc (av cc = dv cc1 = dv cc2 = v cc ) (see note 1) msp430f43x(1), msp430f44x(1) 2.7 3.6 v supply voltage, v ss (av ss = dv ss1 = dv ss2 = v ss ) 0 0 v operating free-air temperature range, t a msp430x43x(1), msp430x44x(1) ?40 85 c lf selected, xts_fll=0 watch crystal 32.768 khz lfxt1 crystal frequency, f (lfxt1) (see note 3) xt1 selected, xts_fll=1 ceramic resonator 450 8000 khz (see note 3) xt1 selected, xts_fll=1 crystal 1000 8000 khz xt2 crystal frequency f ceramic resonator 450 8000 khz xt2 crystal frequency, f (xt2) crystal 1000 8000 khz processor frequency (signal mclk) f v cc = 1.8 v dc 4.15 mhz processor frequency (signal mclk), f (system) v cc = 3.6 v dc 8 mhz notes: 1. it is recommended to power av cc and dv cc from the same source. a maximum difference of 0.3 v between av cc and dv cc can be tolerated during power up and operation. 2. the minimum operating supply voltage is defined according to the trip point where por is going active by decreasing the suppl y voltage. por is going inactive when the supply voltage is raised above the minimum supply voltage plus the hysteresis of the svs circuitry. 3. in lf mode, the lfxt1 oscillator requires a watch crystal. in xt1 mode, lfxt1 accepts a ceramic resonator or a crystal. 1.8 3.6 2.7 3 ????? ????? ????? ????? ????? ????? ????? ?????
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 38 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) supply current into av cc + dv cc excluding external current parameter test conditions v cc min typ max unit i active mode (see note 1), f (mclk) = f (smclk) = 1 mhz, t 40 cto85 c 2.2 v 280 350 a i (am) f (mclk) = f (smclk) = 1 mhz , f (aclk) = 32768 hz xts_fll=0, selm=(0,1) t a = ?40 c to 85 c 3 v 420 560 a i low-power mode, (lpm0) t 40 cto85 c 2.2 v 32 45 a i (lpm0) low power mode , (lpm0) (see note 1 and note 4) t a = ?40 c to 85 c 3 v 55 70 a i low-power mode, (lpm2), f ( mclk ) = f ( smclk ) = 0 mhz, t 40 cto85 c 2.2 v 11 14 a i (lpm2) f(mclk) = f (smclk) = 0 mhz , f(aclk) = 32768 hz, scg0 = 0 (see note 2 and note 4) t a = ?40 c to 85 c 3 v 17 22 a t a = ?40 c 1 1.5 t a = 25 c 22v 1.1 1.5 a low-power mode, (lpm3) f (mclk) =f (smclk) = 0 mhz t a = 60 c 2.2 v 2 3 a i f (mclk) = f (smclk) = 0 mhz, f (aclk) = 32 , 768 hz , scg0 = 1 t a = 85 c 3.5 6 i (lpm3) f (aclk) = 32 , 768 hz , scg0 = 1 (see note 3 and note 4) t a = ?40 c 1.8 2.2 () t a = 25 c 3v 1.6 1.9 a t a = 60 c 3 v 2.5 3.5 a t a = 85 c 4.2 7.5 t a = ?40 c 0.1 0.5 t a = 25 c 22v 0.1 0.5 a low-power mode (lpm4) t a = 60 c 2.2 v 0.7 1.1 a i l ow-power mo d e, (lpm4) f (mclk) = 0 mhz, f (smclk) = 0 mhz, t a = 85 c 1.7 3 i (lpm4) f (mclk) = 0 mhz , f (smclk) = 0 mhz , f (aclk) = 0 hz, scg0 = 1 ( nt2 dnt4) t a = ?40 c 0.1 0.5 (aclk) (see note 2 and note 4) t a = 25 c 3v 0.1 0.5 a t a = 60 c 3 v 0.8 1.2 a t a = 85 c 1.9 3.5 notes: 1. timer_b is clocked by f (dcoclk) = f (dco) = 1 mhz. all inputs are tied to 0 v or to v cc . outputs do not source or sink any current. 2. all inputs are tied to 0 v or to v cc . outputs do not source or sink any current. 3. all inputs are tied to 0 v or to v cc . outputs do not source or sink any current. the current consumption in lpm3 is measured with active basic timer1 and lcd (aclk selected). the current consumption of the comparator_a and the svs module are specified in the respective sections. the lpm3 currents are characterized with a kds daishinku dt?38 (6 pf) crystal and osccapx=1h. 4. current consumption for brownout included. current consumption of active mode versus system frequency i (am) = i (am) [1 mhz] f (system) [mhz] current consumption of active mode versus supply voltage i (am) = i (am) [3 v] + 175 a/v (v cc ? 3 v)
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 39 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) schmitt-trigger inputs ? ports p1, p2, p3, p4, p5, p6 parameter v cc min typ max unit v positive going input threshold voltage 2.2 v 1.1 1.5 v v it+ positive-going input threshold voltage 3 v 1.5 1.9 v v negative going input threshold voltage 2.2 v 0.4 0.9 v v it? negative-going input threshold voltage 3 v 0.9 1.3 v v input voltage hysteresis (v v ) 2.2 v 0.3 1.1 v v hys input voltage hysteresis (v it+ ? v it? ) 3 v 0.5 1 v standard inputs ? rst /nmi, jtag (tck, tms, tdi/tclk) parameter v cc min typ max unit v il low-level input voltage 22v/3v v ss v ss +0.6 v v ih high-level input voltage 2.2 v / 3 v 0.8 v cc v cc v inputs px.x, tax, tbx parameter test conditions v cc min typ max unit p t p1 p2 p1 t p2 t l t i i l 2.2 v/3 v 1.5 cycle t (int) external interrupt timing port p1, p2: p1.x to p2.x, external trigger signal for the interrupt flag, (see note 1) 2.2 v 62 ns (int) pg for the interrupt flag , (see note 1) 3 v 50 ns timer a timer b capture ta0, ta1, ta2 2.2 v 62 t (cap) timer_a, timer_b capture timing tb0, tb1, tb2, tb3, tb4, tb5, tb6 (see note 2) 3 v 50 ns f (taext) timer_a, timer_b clock frequency externally applied taclk tbclk inclk: t =t 2.2 v 8 mhz f (tbext) frequency externally applied to pin taclk, tbclk, inclk: t (h) = t (l) 3 v 10 mhz f (taint) timer_a, timer_b clock smclk or aclk signal selected 2.2 v 8 mhz f (tbint) timer _ a, timer _ b clock frequency smclk or aclk signal selected 3 v 10 mhz notes: 1. the external signal sets the interrupt flag every time the minimum t (int) cycle and time parameters are met. it may be set even with trigger signals shorter than t (int) . both the cycle and timing specifications must be met to ensure the flag is set. t (int) is measured in mclk cycles. 2. seven capture/compare registers in ?x44x(1) and three capture/compare registers in ?x43x(1). leakage current (see notes 1 and 2) parameter test conditions v cc min typ max unit i lkg(p1.x) port p1 port 1: v (p1.x) 50 i lkg(p2.x) port p2 port 2: v (p2.x) 50 i lkg(p3.x) leaka g e port p3 port 3: v (p3.x) 2 2 v/3 v 50 na i lkg(p4.x) leakage current port p4 port 4: v (p4.x) 2.2 v/3 v 50 na i lkg(p5.x) port p5 port 5: v (p5.x) 50 i lkg(p6.x) port p6 port 6: v (p6.x) 50 notes: 1. the leakage current is measured with v ss or v cc applied to the corresponding pin(s), unless otherwise noted. 2. the port pin must be selected as input and there must be no optional pullup or pulldown resistor.
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 40 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) outputs ? ports p1, p2, p3, p4, p5, p6 parameter test conditions v cc min typ max unit i oh(max) = ?1.5 ma (see note 1) 2.2 v v cc ?0.25 v cc v high level output voltage i oh(max) = ?6 ma (see note 2) 2.2 v v cc ?0.6 v cc v v oh high-level output voltage i oh(max) = ?1.5 ma (see note 1) 3 v v cc ?0.25 v cc v i oh(max) = ?6 ma (see note 2) 3 v v cc ?0.6 v cc i ol(max) = 1.5 ma (see note 1) 2.2 v v ss v ss +0.25 v low level output voltage i ol(max) = 6 ma (see note 2) 2.2 v v ss v ss +0.6 v v ol low-level output voltage i ol(max) = 1.5 ma (see note 1) 3 v v ss v ss +0.25 v i ol(max) = 6 ma (see note 2) 3 v v ss v ss +0.6 notes: 1. the maximum total current, i oh(max) and i ol(max), for all outputs combined, should not exceed 12 ma to satisfy the maximum specified voltage drop. 2. the maximum total current, i oh(max) and i ol(max), for all outputs combined, should not exceed 48 ma to satisfy the maximum specified voltage drop. output frequency parameter test conditions min typ max unit f (1 x 60 y 7) c l = 20 pf, v cc = 2.2 v dc 5 mhz f (px.y) (1 x 6, 0 y 7) c l = 20 pf , i l = 1.5 ma v cc = 3 v dc 7.5 mhz f (aclk) p1.1/ta0/mclk, f (mclk) p1 . 1/ta0/mclk , p1.5/taclk/aclk c l = 20 pf f ( s y stem ) mhz f (smclk) p1.5/taclk/aclk p1.4/tbclk/smclk c l 20 pf f (system) mhz p1.5/taclk/aclk, f (aclk) = f (lfxt1) = f (xt1) 40% 60% p1 . 5/taclk/aclk , c l = 20 pf f (aclk) = f (lfxt1) = f (lf) 30% 70% c l 20 pf v cc = 2.2 v / 3 v f (aclk) = f (lfxt1) 50% p1.1/ta0/mclk , f (mclk) = f (xt1) 40% 60% t (xdc) duty cycle of output frequency p1 . 1/ta0/mclk , c l = 20 pf, v cc = 2.2 v / 3 v f (mclk) = f (dcoclk) 50%? 15 ns 50% 50%+ 15 ns p1.4/tbclk/smclk , f (smclk) = f (xt2) 40% 60% p1 . 4/tbclk/smclk , c l = 20 pf, v cc = 2.2 v / 3 v f (smclk) = f (dcoclk) 50%? 15 ns 50% 50%+ 15 ns
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 41 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) outputs ? ports p1, p2, p3, p4, p5, and p6 (continued) figure 2 v ol ? low-level output voltage ? v 0 2 4 6 8 10 12 14 16 0.0 0.5 1.0 1.5 2.0 2.5 v cc = 2.2 v p2.7 typical low-level output current vs low-level output voltage t a = 25 c t a = 85 c ol i ? typical low-level output current ? ma figure 3 v ol ? low-level output voltage ? v 0 5 10 15 20 25 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v cc = 3 v p2.7 typical low-level output current vs low-level output voltage t a = 25 c t a = 85 c ol i ? typical low-level output current ? ma figure 4 v oh ? high-level output voltage ? v ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 0.0 0.5 1.0 1.5 2.0 2.5 v cc = 2.2 v p2.7 typical high-level output current vs high-level output voltage t a = 25 c t a = 85 c ol i ? typical high-level output current ? ma figure 5 v oh ? high-level output voltage ? v ?30 ?25 ?20 ?15 ?10 ?5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v cc = 3 v p2.7 typical high-level output current vs high-level output voltage t a = 25 c t a = 85 c ol i ? typical high-level output current ? ma
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 42 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) wake-up lpm3 parameter test conditions v cc min typ max unit f = 1 mhz 6 t d ( lpm3 ) delay time f = 2 mhz 2.2 v/3 v 6 s t d(lpm3) delay time f = 3 mhz 2.2 v/3 v 6 s ram parameter test conditions min typ max unit vramh cpu halted (see note 1) 1.6 v note 1: this parameter defines the minimum supply voltage when the data in program memory ram remain unchanged. no program execution should take place during this supply voltage condition. lcd parameter test conditions min typ max unit v (33) voltage at p5.7/r33 2.5 v cc + 0.2 v (23) analog voltage voltage at p5.6/r23 v 3v [v (33) ?v (03) ] 2/3 + v (03) v v (13) analog voltage voltage at p5.5/r13 v cc = 3 v [v (33) ?v (03) ] 1/3 + v (03) v v (33) ? v (03) voltage at r33 to r03 2.5 v cc + 0.2 i (r03) r03 = v ss no load at all 20 i (r13) input leakage p5.5/r13 = v cc /3 segment and common lines 20 na i (r23) pg p5.6/r23 = 2 v cc /3 common li nes, v cc = 3 v 20 v (sxx0) v (03) v (03) ? 0.1 v (sxx1) se g ment line i =3 a v =3v v (13) v (13) ? 0.1 v v (sxx2) segment line voltage i (sxx) = ?3 a, v cc = 3 v v (23) v (23) ? 0.1 v v (sxx3) v (33) v (33) + 0.1
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 43 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) comparator_a (see note 1) parameter test conditions v cc min typ max unit i caon 1 carsel 0 caref 0 2.2 v 25 40 a i (cc) caon=1, carsel=0, caref=0 3 v 45 60 a i caon=1, carsel=0, caref=1/2/3, 2.2 v 30 50 a i (refladder/refdiode) caon=1 , carsel=0 , caref=1/2/3 , no load at p1.6/ca0 and p1.7/ca1 3 v 45 71 a v (ref025) voltage @ 0.25 v cc node v cc pca0=1, carsel=1, caref=1, no load at p1.6/ca0 and p1.7/ca1 2.2 v / 3 v 0.23 0.24 0.25 v (ref050) voltage @ 0.5 v cc node v cc pca0=1, carsel=1, caref=2, no load at p1.6/ca0 and p1.7/ca1 2.2v / 3 v 0.47 0.48 0.5 v see figure 6 and figure 7 pca0=1, carsel=1, caref=3, no load at p1 6/ca0 and p1 7/ca1; 2.2 v 390 480 540 mv v (refvt) see figure 6 and figure 7 no load at p1.6/ca0 and p1.7/ca1; t a = 85 c 3 v 400 490 550 mv v ic common-mode input voltage range caon=1 2.2 v / 3 v 0 v cc ?1 v v p ?v s offset voltage see note 2 2.2 v / 3 v ?30 30 mv v hys input hysteresis caon = 1 2.2 v / 3 v 0 0.7 1.4 mv t a = 25 c, 2.2 v 160 210 300 ns t t a = 25 c , overdrive 10 mv, without filter: caf = 0 3 v 80 150 240 ns t (response lh) t a = 25 c 2.2 v 1.4 1.9 3.4 s t a = 25 c overdrive 10 mv, with filter: caf = 1 3 v 0.9 1.5 2.6 s t a = 25 c 2.2 v 130 210 300 ns t t a = 25 c overdrive 10 mv, without filter: caf = 0 3 v 80 150 240 ns t (response hl) t a = 25 c, 2.2 v 1.4 1.9 3.4 s t a = 25 c , overdrive 10 mv, with filter: caf = 1 3 v 0.9 1.5 2.6 s notes: 1. the leakage current for the comparator_a terminals is identical to i lkg(px.x) specification. 2. the input offset voltage can be cancelled by using the caex bit to invert the comparator_a inputs on successive measurements. the two successive measurements are then summed together.
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 44 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) typical characteristics t a ? free-air temperature ? c 400 450 500 550 600 650 ?45 ?25 ?5 15 35 55 75 95 v cc = 3 v figure 6. v ( refvt ) vs temperature v ref ? reference voltage ? mv typical reference voltage vs free-air temperature figure 7. v ( refvt ) vs temperature t a ? free-air temperature ? c 400 450 500 550 600 650 ?45 ?25 ?5 15 35 55 75 95 v cc = 2.2 v typical reference voltage vs free-air temperature v ref ? reference voltage ? mv _ + caon 0 1 v+ 0 1 caf low-pass filter 2 s to internal modules set caifg flag caout v? v cc 1 0 v 0 figure 8. block diagram of comparator_a module overdrive v caout t (response) v+ v? 400 mv figure 9. overdrive definition
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 45 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) por/brownout reset (bor) (see note 1) parameter test conditions min typ max unit t d(bor) 2000 s v cc(start) dv cc /dt 3 v/s (see figure 10) 0.7 v (b_it?) v v (b_it?) brownout dv cc /dt 3 v/s (see figure 10 through figure 12) 1.71 v v hys(b_it?) (see note 2) dv cc /dt 3 v/s (see figure 10) 70 130 180 mv t (reset) pulse length needed at rst /nmi pin to accepted reset internally, v cc = 2.2 v/3 v 2 s notes: 1. the current consumption of the brownout module is already included in the i cc current consumption data. the voltage level v (b_it?) + v hys(b_it?) is 1.8v. 2. during power up, the cpu begins code execution following a period of t d(bor) after v cc = v (b_it?) + v hys(b_it?) . the default fll+ settings must not be changed until v cc v cc(min) , where v cc(min) is the minimum supply voltage for the desired operating frequency. see the msp430x4xx family user?s guide (slau056) for more information on the brownout/svs circuit. typical characteristics 0 1 t d(bor) v cc v (b_it?) v hys(b_it?) v cc(start) figure 10. por/brownout reset (bor) vs supply voltage v cc(drop) v cc 3 v t pw 0 0.5 1 1.5 2 0.001 1 1000 typical conditions 1 ns 1 ns t pw ? pulse width ? st pw ? pulse width ? s v cc = 3 v v cc(drop) ? v figure 11. v cc(drop) level with a square voltage drop to generate a por/brownout signal
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 46 post office box 655303 ? dallas, texas 75265 typical characteristics (continued) v cc 0 0.5 1 1.5 2 v cc(drop) t pw t pw ? pulse width ? s 3 v 0.001 1 1000 t f t r t pw ? pulse width ? s t f = t r typical conditions v cc = 3 v v cc(drop) ? v figure 12. v cc(drop) level with a triangle voltage drop to generate a por/brownout signal electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) supply voltage supervisor/monitor (svs) parameter test conditions min nom max unit t dv cc /dt > 30 v/ms (see figure 13) 5 150 s t (svsr) dv cc /dt 30 v/ms 2000 s t d(svson) svson, switch from vld=0 to vld 0, v cc = 3 v 20 150 s t settle vld 0 ? 12 s v (svsstart) vld 0, v cc /dt 3 v/s (see figure 13) 1.55 1.7 v vld = 1 70 120 155 mv v h y s ( svs_it? ) v cc /dt 3 v/s (see figure 13) vld = 2 to 14 v (svs_it?) 0.004 v (svs_it?) 0.008 v hys(svs _ it ? ) v cc /dt 3 v/s (see figure 13), external voltage applied on a7 vld = 15 4.4 10.4 mv vld = 1 1.8 1.9 2.05 vld = 2 1.94 2.1 2.25 vld = 3 2.05 2.2 2.37 vld = 4 2.14 2.3 2.48 vld = 5 2.24 2.4 2.6 vld = 6 2.33 2.5 2.71 v /dt 3 v/s (see figure 13) vld = 7 2.46 2.65 2.86 v (svs it ) v cc /dt 3 v/s (see figure 13) vld = 8 2.58 2.8 3 v v (svs_it?) vld = 9 2.69 2.9 3.13 v vld = 10 2.83 3.05 3.29 vld = 11 2.94 3.2 3.42 vld = 12 3.11 3.35 3.61 ? vld = 13 3.24 3.5 3.76 ? vld = 14 3.43 3.7 ? 3.99 ? v cc /dt 3 v/s (see figure 13), external voltage applied on a7 vld = 15 1.1 1.2 1.3 i cc(svs) (see note 3) vld 0, v cc = 2.2 v/3 v 10 15 a ? the recommended operating voltage range is limited to 3.6 v. ? t settle is the settling time that the comparator o/p needs to have a stable level after vld is switched vld 0 to a different vld value somewhere between 2 and 15. the overdrive is assumed to be > 50 mv. note 3: the current consumption of the svs module is not included in the i cc current consumption data.
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 47 post office box 655303 ? dallas, texas 75265 typical characteristics v cc(start) v cc v (b_it?) brownout region v (svsstart) v (svs_it?) software sets vld>0: svs is active t d(svsr) undefined v hys(svs_it?) 0 1 t d(bor) brownout 0 1 t d(svson) t d(bor) 0 1 set por brown- out region svs circuit is active from vld > to v cc < v( b_it?) svs out v hys(b_it?) figure 13. svs reset (svsr) vs supply voltage 0 0.5 1 1.5 2 v cc v cc 1 ns 1 ns v cc(drop) t pw t pw ? pulse width ? s v cc(drop) ? v 3 v 1 10 1000 t f t r t ? pulse width ? s 100 t pw 3 v t f = t r rectangular drop triangular drop v cc(drop) figure 14. v cc(drop) with a square voltage drop and a triangle voltage drop to generate an svs signal
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 48 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) dco parameter test conditions min typ max unit f (dcoclk) n (dco) =01eh, fn_8=fn_4=fn_3=fn_2=0, d = 2; dcoplus= 0, f crystal = 32.768 khz v cc = 2.2 v/3 v 1 mhz f fn 8 fn 4 fn 3 fn 2 0; dcoplus 1 v cc = 2.2 v 0.3 0.65 1.25 mhz f (dco=2) fn_8=fn_4=fn_3=fn_2=0; dcoplus = 1 v cc = 3 v 0.3 0.7 1.3 mhz f fn 8 fn 4 fn 3 fn 2 0; dcoplus 1 v cc = 2.2 v 2.5 5.6 10.5 mhz f (dco=27) fn_8=fn_4=fn_3=fn_2=0; dcoplus = 1 v cc = 3 v 2.7 6.1 11.3 mhz f fn_8=fn_4=fn_3=0, fn_2=1; dcoplus = 1 v cc = 2.2 v 0.7 1.3 2.3 mhz f (dco=2) fn _ 8=fn _ 4=fn _ 3=0 , fn _ 2=1; dcoplus = 1 v cc = 3 v 0.8 1.5 2.5 mhz f fn 8 fn 4 fn 3 0 fn 2 1; dcoplus 1 v cc = 2.2 v 5.7 10.8 18 mhz f (dco=27) fn_8=fn_4=fn_3=0, fn_2=1; dcoplus = 1 v cc = 3 v 6.5 12.1 20 mhz f fn 8 fn 4 0 fn 3 1 fn 2 x; dcoplus 1 v cc = 2.2 v 1.2 2 3 mhz f (dco=2) fn_8=fn_4=0, fn_3= 1, fn_2=x; dcoplus = 1 v cc = 3 v 1.3 2.2 3.5 mhz f fn 8 fn 4 0 fn 3 1 fn 2 x; dcoplus 1 v cc = 2.2 v 9 15.5 25 mhz f (dco=27) fn_8=fn_4=0, fn_3= 1, fn_2=x; dcoplus = 1 v cc = 3 v 10.3 17.9 28.5 mhz f fn 8 0 fn 4 1 fn 3 fn 2 x; dcoplus 1 v cc = 2.2 v 1.8 2.8 4.2 mhz f (dco=2) fn_8=0, fn_4= 1, fn_3= fn_2=x; dcoplus = 1 v cc = 3 v 2.1 3.4 5.2 mhz f fn 8 0 fn 4 1 fn 3 fn 2 x; dcoplus 1 v cc = 2.2 v 13.5 21.5 33 mhz f (dco=27) fn_8=0, fn_4=1, fn_3= fn_2=x; dcoplus = 1 v cc = 3 v 16 26.6 41 mhz f fn 8 1 fn 4 fn 3 fn 2 x; dcoplus 1 v cc = 2.2 v 2.8 4.2 6.2 mhz f (dco=2) fn_8=1, fn_4=fn_3=fn_2=x; dcoplus = 1 v cc = 3 v 4.2 6.3 9.2 mhz f fn 8 1 fn 4 fn 3 fn 2 x; dcoplus 1 v cc = 2.2 v 21 32 46 mhz f (dco=27) fn_8=1,fn_4=fn_3=fn_2=x; dcoplus = 1 v cc = 3 v 30 46 70 mhz s step size between adjacent dco taps: 1 < tap 20 1.06 1.11 s n step size between adjacent dco taps: s n = f dco(tap n+1) / f dco(tap n) , (see figure 16 for taps 21 to 27) tap = 27 1.07 1.17 d t temperature drift, n ( d co) = 01eh, fn_8=fn_4=fn_3=fn_2=0 v cc = 2.2 v ?0.2 ?0.3 ?0.4 % / c d t temperature drift , n (dco) = 01eh , fn _ 8=fn _ 4=fn _ 3=fn _ 2=0 d = 2; dcoplus = 0 v cc = 3 v ?0.2 ?0.3 ?0.4 % / c d v drift with v cc variation, n (dco) = 01eh, fn_8=fn_4=fn_3=fn_2=0, d= 2; dcoplus = 0 v cc = 2.2 v/3 v 0 5 15 %/v t a ? c v cc ? v f (dco) f (dco20 c) f (dco) f (dco3v) 1.8 3.0 2.4 3.6 1.0 20 60 40 85 1.0 0 ?20 ?40 0 figure 15. dco frequency vs supply voltage v cc and vs ambient temperature
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 49 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ?????????????
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 50 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) crystal oscillator, lfxt1 oscillator (see notes 1 and 2) parameter test conditions v cc min typ max unit osccapx = 0h 2.2 v / 3 v 0 c xin inte g rated in p ut ca p acitance osccapx = 1h 2.2 v/3 v 10 p f c xin integrated input capacitance osccapx = 2h 2.2 v/3 v 14 pf osccapx = 3h 2.2 v/3 v 18 osccapx = 0h 2.2 v/3 v 0 c integrated output capacitance osccapx = 1h 2.2 v/3 v 10 pf c xout integrated output capacitance osccapx = 2h 2.2 v/3 v 14 pf osccapx = 3h 2.2 v/3 v 18 v il input levels at xin see note 3 2 2 v/3 v v ss 0.2 v cc v v ih input levels at xin see note 3 2.2 v/3 v 0.8 v cc v cc v notes: 1. the parasitic capacitance from the package and board may be estimated to be 2 pf. the effective load capacitor for the crystal is (c xin xc xout ) / (c xin + c xout ). this is independent of xts_fll. 2. to improve emi on the low-power lfxt1 oscillator, particularly in the lf mode (32 khz), the following guidelines should be ob served. ? keep the trace between the ?f43x(1)/44x(1) and the crystal as short as possible. ? design a good ground plane around the oscillator pins. ? prevent crosstalk from other clock or data lines into oscillator pins xin and xout. ? avoid running pcb traces underneath or adjacent to the xin and xout pins. ? use assembly materials and praxis to avoid any parasitic load on the oscillator xin and xout pins. ? if conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. ? do not route the xout line to the jtag header to support the serial programming adapter as shown in other documentation. this signal is no longer required for the serial programming adapter. 3. applies only when using an external logic-level clock source. xts_fll must be set. not applicable when using a crystal or resonator. 4. external capacitance is recommended for precision real-time clock applications; osccapx = 0h. crystal oscillator, xt2 oscillator (see note 1) parameter test conditions min nom max unit c xt2in integrated input capacitance v cc = 2.2 v/3 v 2 pf c xt2out integrated output capacitance v cc = 2.2 v/3 v 2 pf v il input levels at xt2in v = 2 2 v/3 v (see note 2) v ss 0.2 v cc v v ih input levels at xt2in v cc = 2.2 v/3 v (see note 2) 0.8 v cc v cc v notes: 1. the oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer. 2. applies only when using an external logic-level clock source. not applicable when using a crystal or resonator. usart0, usart1 (see note 1) parameter test conditions min nom max unit t usart0/1: deglitch time v cc = 2.2 v, sync = 0, uart mode 200 430 800 ns t ( ) usart0/1: deglitch time v cc = 3 v, sync = 0, uart mode 150 280 500 ns note 1: the signal applied to the usart0/1 receive signal/terminal (urxd0/1) should meet the timing requirements of t ( ) to ensure that the urxs flip-flop is set. the urxs flip-flop is set with negative pulses meeting the minimum-timing condition of t ( ) . the operating conditions to set the flag must be met independently from this timing constraint. the deglitch circuitry is active only on nega tive transitions on the urxd0/1 line.
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 51 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit adc, power supply and input range conditions (see note 1) parameter test conditions v cc min nom max unit av cc analog supply voltage av cc and dv cc are connected together, av ss and dv ss are connected together, v (avss) = v (dvss) = 0 v 2.2 3.6 v v (p6.x/ax) analog input voltage range (see note 2) all p6.0/a0 to p6.7/a7 terminals. analog inputs selected in adc12mctlx register and p6sel.x=1, 0 x 7; v (avss) v p6.x/ax v (avcc) 0 v avcc v i operating supply current into av terminal f adc12clk = 5.0 mhz adc12on 1 refon 0 2.2 v 0.65 1.3 ma i adc12 into av cc terminal (see note 3) adc12on = 1, refon = 0 sht0=0, sht1=0, adc12div=0 3 v 0.8 1.6 ma i operating supply current it av til f adc12clk = 5.0 mhz adc12on = 0, refon = 1, ref2_5v = 1 3 v 0.5 0.8 ma i ref+ into av cc terminal (see note 4) f adc12clk = 5.0 mhz adc12on 0 2.2 v 0.5 0.8 ma (see note 4) adc12on = 0, refon = 1, ref2_5v = 0 3 v 0.5 0.8 ma c i input capacitance only one terminal can be selected at one time, p6.x/ax 2.2 v 40 pf r i input mux on resistance 0v v ax v avcc 3 v 2000 ? notes: 1. the leakage current is defined in the leakage current table with p6.x/ax parameter. 2. the analog input voltage range must be within the selected reference voltage range v r+ to v r? for valid conversion results. 3. the internal reference supply current is not included in current consumption parameter i adc12 . 4. the internal reference current is supplied via terminal av cc . consumption is independent of the adc12on control bit, unless a conversion is active. the refon bit enables to settle the built-in reference before starting an a/d conversion. 12-bit adc, external reference (see note 1) parameter test conditions v cc min nom max unit v eref+ positive external reference voltage input v eref+ > v ref? /v eref? (see note 2) 1.4 v avcc v v ref? / v eref? negative external reference voltage input v eref+ > v ref? /v eref? (see note 3) 0 1.2 v (v eref+ ? v ref?/ v eref? ) differential external reference voltage input v eref+ > v ref? /v eref? (see note 4) 1.4 v avcc v i veref+ static input current 0v v eref+ v avcc 2.2 v/3 v 1 a i vref?/veref? static input current 0v v eref? v avcc 2.2 v/3 v 1 a notes: 1. the external reference is used during conversion to charge and discharge the capacitance array. the input capacitance, c i , is also the dynamic load for an external reference during conversion. the dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy. 2. the accuracy limits the minimum positive external reference voltage. lower reference voltage levels may be applied with reduc ed accuracy requirements. 3. the accuracy limits the maximum negative external reference voltage. higher reference voltage levels may be applied with redu ced accuracy requirements. 4. the accuracy limits minimum external differential reference voltage. lower differential reference voltage levels may be appli ed with reduced accuracy requirements.
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 52 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit adc, built-in reference parameter test conditions v cc min typ max unit v positive built-in reference volta g e ref2_5v = 1 for 2.5 v i vref+ i vref+ max 3 v 2.4 2.5 2.6 v v ref+ positive built in reference voltage output ref2_5v = 0 for 1.5 v i vref+ i vref+ max 2.2 v/3 v 1.44 1.5 1.56 v av i i lt p iti ref2_5v = 0, i vref+ 1ma 2.2 av cc ( min ) av cc minimum voltage, positive built - in reference active ref2_5v = 1, i vref+ 0.5ma v ref+ + 0.15 v av cc(min) b u ilt - i n re f erence ac ti ve ref2_5v = 1, i vref+ 1ma v ref+ + 0.15 v i load current out of v terminal 2.2 v 0.01 ?0.5 ma i vref+ load current out of v ref+ terminal 3 v ?1 ma i vref+ = 500 a +/? 100 a analog input voltage 0 75 v; 2.2 v 2 lsb i load-current re g ulation v ref+ analog input voltage ~0.75 v; ref2_5v = 0 3 v 2 lsb i l(vref)+ load current regulation v ref + terminal i vref+ = 500 a 100 a analog input voltage ~1.25 v; ref2_5v = 1 3 v 2 lsb i load current re g ulation v ref+ i vref+ =100 a 900 a, c 5 f ax 05xv 3v 20 ns i dl(vref) + load current regulation v ref + terminal c vref+ =5 f, ax ~0.5 x v ref+ error of conversion result 1 lsb 3 v 20 ns c vref+ capacitance at pin v ref+ (see note 1) refon =1, 0 ma i vref+ i vref+ max 2.2 v/3 v 5 10 f t ref+ temperature coefficient of built-in reference i vref+ is a constant in the range of 0 ma i vref+ 1 ma 2.2 v/3 v 100 ppm/ c t refon settle time of internal reference voltage (see figure 18 and note 2) i vref+ = 0.5 ma, c vref+ = 10 f, v ref+ = 1.5 v 2.2 v 17 ms notes: 1. the internal buffer operational amplifier and the accuracy specifications require an external capacitor. all inl and dn l tests uses two capacitors between pins v ref+ and av ss and v ref? /v eref? and av ss : 10 f tantalum and 100 nf ceramic. 2. the condition is that the error in a conversion started after t refon is less than 0.5 lsb. the settling time depends on the external capacitive load. c vref+ 1 f 0 1 ms 10 ms 100 ms t refon t refon .66 x c vref+ [ms] with c vref+ in f 100 f 10 f figure 18. typical settling time of internal reference t refon vs external capacitor on v ref +
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 53 post office box 655303 ? dallas, texas 75265 + ? 10 f 100 nf av ss msp430f43x msp430f44x + ? + ? 10 f 100 nf 10 f 100 nf av cc 10 f 100 nf dv ss1 dv cc1 from power supply apply external reference + ? apply external reference [v eref+ ] or use internal reference [v ref+ ] v ref+ or v eref+ v ref ?/v eref? /dv cc2 /dv ss2 figure 19. supply voltage and reference voltage design v ref?/ v eref? external supply + ? 10 f 100 nf av ss msp430f43x msp430f44x + ? 10 f 100 nf av cc 10 f 100 nf from power supply + ? apply external reference [v eref+ ] or use internal reference [v ref+ ] v ref+ or v eref+ v ref? /v eref? reference is internally switched to av ss dv ss1 dv cc1 /dv cc2 /dv ss2 figure 20. supply voltage and reference voltage design v ref?/ v eref? = av ss , internally connected
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 54 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit adc, timing parameters parameter test conditions v cc min typ max unit f adc12clk for specified performance of adc12 linearity parameters 2.2v/3 v 0.45 5 6.3 mhz f adc12osc internal adc12 oscillator adc12div=0, f adc12clk =f adc12osc 2.2 v/ 3 v 3.7 6.3 mhz t conversion time c vref+ 5 f, internal oscillator, f adc12osc = 3.7 mhz to 6.3 mhz 2.2 v/ 3 v 2.06 3.51 s t convert conversion time external f adc12clk from aclk, mclk or smclk: adc12ssel 0 13 adc12div 1/f adc12clk s t adc12on turn on settling time of the adc see note 1 100 ns t sampling time r s = 400 ? , r i = 1000 ? , c 30 pf 3 v 1220 ns t sample sampling time c i = 30 pf = [r s + r i ] x c i; (see note 2) 2.2 v 1400 ns notes: 1. the condition is that the error in a conversion started after t adc12on is less than 0.5 lsb. the reference and input signal are already settled. 2. approximately ten tau ( ) are needed to get an error of less than 0.5 lsb: t sample = ln(2 n+1 ) x (r s + r i ) x c i + 800 ns where n = adc resolution = 12, r s = external source resistance. 12-bit adc, linearity parameters parameter test conditions v cc min typ max unit e integral linearity error 1.4 v (v eref+ ? v ref? /v eref? ) min 1.6 v 2 2 v/3 v 2 lsb e i integral linearity error 1.6 v < (v eref+ ? v ref? /v eref? ) min [v (avcc) ] 2.2 v/3 v 1.7 lsb e d differential linearity error (v eref+ ? v ref? /v eref? ) min (v eref+ ? v ref? /v eref? ), c vref+ = 10 f (tantalum) and 100 nf (ceramic) 2.2 v/3 v 1 lsb e o offset error (v eref+ ? v ref? /v eref? ) min (v eref+ ? v ref? /v eref? ), internal impedance of source r s < 100 ? , c vref+ = 10 f (tantalum) and 100 nf (ceramic) 2.2 v/3 v 2 4 lsb e g gain error (v eref+ ? v ref? /v eref? ) min (v eref+ ? v ref? /v eref? ), c vref+ = 10 f (tantalum) and 100 nf (ceramic) 2.2 v/3 v 1.1 2 lsb e t total unadjusted error (v eref+ ? v ref? /v eref? ) min (v eref+ ? v ref? /v eref? ), c vref+ = 10 f (tantalum) and 100 nf (ceramic) 2.2 v/3 v 2 5 lsb
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 55 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit adc, temperature sensor and built-in v mid parameter test conditions v cc min typ max unit i operatin g suppl y current into refon = 0, inch = 0ah, 2.2 v 40 120 a i sensor operating supply current into av cc terminal (see note 1) refon = 0 , inch = 0ah , adc12on=na, t a = 25 c 3 v 60 160 a v adc12on = 1, inch = 0ah, 2.2 v 986 986 5% mv v sensor adc12on = 1 , inch = 0ah , t a = 0 c 3 v 986 986 5% mv tc adc12on 1 inch 0ah 2.2 v 3.55 3.55 3% mv/ c tc sensor adc12on = 1, inch = 0ah 3 v 3.55 3.55 3% mv/ c t sample time required if channel adc12on = 1, inch = 0ah, 2.2 v 30 s t sensor(sample) sample time required if channel 10 is selected (see note 2) adc12on = 1 , inch = 0ah , error of conversion result 1 lsb 3 v 30 s i current into divider at channel 11 adc12on = 1, inch = 0bh, 2.2 v na a i vmid current into divider at channel 11 adc12on = 1 , inch = 0bh , (see note 3) 3 v na a v av divider at channel 11 adc12on = 1, inch = 0bh, 2.2 v 1.1 1.1 0.04 v v mid av cc divider at channel 11 adc12on = 1 , inch = 0bh , v mid is ~0.5 x v avcc 3 v 1.5 1.50 0.04 v t sample time required if channel adc12on = 1, inch = 0bh, 2.2 v 1400 ns t vmid(sample) sample time required if channel 11 is selected (see note 4) adc12on = 1 , inch = 0bh , error of conversion result 1 lsb 3 v 1220 ns notes: 1. the sensor current i sensor is consumed if (adc12on = 1 and refon=1), or (adc12on=1 and inch=0ah and sample signal is high). therefore it includes the constant current through the sensor and the reference. 2. the typical equivalent impedance of the sensor is 51 k ? . the sample time required includes the sensor-on time t sensor(on) . 3. no additional current is needed. the v mid is used during sampling. 4. the on-time t vmid(on) is included in the sampling time t vmid(sample) ; no additional on time is needed.
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 56 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) flash memory parameter test conditions v cc min typ max unit v cc(pgm/ erase) program and erase supply voltage 2.7 3.6 v f ftg flash timing generator frequency 257 476 khz i pgm supply current from dv cc during program 2.7 v/ 3.6 v 3 5 ma i erase supply current from dv cc during erase 2.7 v/ 3.6 v 3 7 ma t cpt cumulative program time see note 1 2.7 v/ 3.6 v 10 ms t cmerase cumulative mass erase time see note 2 2.7 v/ 3.6 v 200 ms program/erase endurance 10 4 10 5 cycles t retention data retention duration t j = 25 c 100 years t word word or byte program time 35 t block, 0 block program time for 1 st byte or word 30 t block, 1-63 block program time for each additional byte or word see note 3 21 t t block, end block program end-sequence wait time see note 3 6 t ftg t mass erase mass erase time 5297 t seg erase segment erase time 4819 notes: 1. the cum ulative program time must not be exceeded when writing to a 64-byte flash block. this parameter applies to all programming methods: individual word/byte write and block write modes. 2. the mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/f ftg ,max = 5297x1/476khz). to achieve the required cumulative mass erase time the flash controller?s mass erase operation can be repeated until this time is met. (a worst case minimum of 19 cycles are required). 3. these values are hardwired into the flash controller?s state machine (t ftg = 1/f ftg ). jtag interface parameter test conditions v cc min typ max unit f tck input frequency see note 1 2.2 v 0 5 mhz f tck tck input frequency see note 1 3 v 0 10 mhz r internal internal pullup resistance on tms, tck, tdi/tclk see note 2 2.2 v/ 3 v 25 60 90 k ? notes: 1. f tck may be restricted to meet the timing requirements of the module selected. 2. tms, tdi/tclk, and tck pull-up resistors are implemented in all versions. jtag fuse (see note 1) parameter test conditions min typ max unit v cc(fb) supply voltage during fuse-blow condition t a = 25 c 2.5 v v fb voltage level on tdi/tclk for fuse-blow: f versions 6 7 v i fb supply current into tdi/tclk during fuse blow 100 ma t fb time to blow fuse 1 ms notes: 1. once the fuse is blown, no further access to the msp430 jt ag/t est and emulation features is possible. the jtag block is switched to bypass mode.
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g january 2002 revised october 2009 57 post office box 655303 ? dallas, texas 75265 application information input/output schematics port p1, p1.0 to p1.5, input/output with schmitt trigger p1out.x module x out p1dir.x direction control from module p1sel.x d en interrupt edge select p1ies.x p1sel.x p1ie.x p1ifg.x p1irq.x p1.x en set q 0 1 1 0 pad logic 0: input 1: output bus keeper capd.x note: 0< x< 5 note: port function is active if capd.x = 0 pnsel.x pndir.x direction from module pnout.x module x out pnin.x pnie.x pnifg.x pnies.x module x in p1sel.1 p1dir.1 p1out.1 p1in.1 p1ie.1 p1ifg.1 p1ies.1 p1sel.2 p1dir.2 p1out.2 p1in.2 p1ie.2 p1ifg.2 p1ies.2 p1sel.3 p1dir.3 p1out.3 p1in.3 p1ie.3 p1ifg.3 p1ies.3 p1sel.4 p1dir.4 p1out.4 p1in.4 p1ie.4 p1ifg.4 p1ies.4 p1sel.5 p1dir.5 p1out.5 p1in.5 p1ie.5 p1ifg.5 p1ies.5 p1sel.0 p1dir.0 p1out.0 p1in.0 p1ie.0 p1ifg.0 p1ies.0 svsout out0 sig. out1 sig. cci0a cci1a tbouth tbclk taclk p1dir.1 p1dir.2 p1dir.3 p1dir.4 p1dir.5 p1dir.0 smclk aclk mclk module x in p1in.x p1.5/taclk/aclk p1.0/ta0 p1.1/ta0/mclk p1.2/ta1 p1.4/tbclk/smclk p1.3/tbouth/svsout cci0b ? ? ? ? ? ? control ? ? ? timer_a ? timer_b
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g january 2002 revised october 2009 58 post office box 655303 ? dallas, texas 75265 application information port p1, p1.6, p1.7, input/output with schmitt trigger p1out.7 p1dir.7 p1sel.7 d en interrupt edge select p1ies.7 p1sel.7 p1ie.7 p1ifg.7 p1irq.07 en set q 0 1 1 0 capd.7 p1out.6 p1dir.6 p1sel.6 d en interrupt edge select p1ies.x p1sel.x p1ie.7 p1ifg.7 p1irq.07 p1.6/ ca0 en set q 0 1 1 0 capd.6 note: port function is active if capd.6 = 0 p1in.6 unused p1.7/ ca1 comparator_a reference block cci1b caf caref p2ca caex caref to timer_ax + 2 avcc ca0 ca1 pad logic 0: input 1: output bus keeper pad logic 0: input 1: output bus keeper p1dir.6 p1dir.7 p1in.7 unused note: port function is active if capd.7 = 0 dv ss dv ss
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 59 post office box 655303 ? dallas, texas 75265 application information port p2, p2.0, p2.4 to p2.5, input/output with schmitt trigger p2out.x module x out p2dir.x direction control from module p2sel.x d en interrupt edge select p2ies.x p2sel.x p2ie.x p2ifg.x p2irq.x en set q 0 1 1 0 pnsel.x pndir.x dir. control from module pnout.x module x out pnin.x pnie.x pnifg.x pnies.x module x in p2sel.4 p2dir.4 p2out.4 p2in.4 p2ie.4 p2ifg.4 p2ies.4 p2sel.5 p2dir.5 p2out.5 p2in.5 p2ie.5 p2ifg.5 p2ies.5 p2sel.0 p2dir.0 p2out.0 p2in.0 p2ie.0 p2ifg.0 p2ies.0 out2 sig. cci2a p2dir.0 utxd0 dvss p2.5/urxd0 p2.0/ta2 p2.4/utxd0 module x in p2in.x x {0,4,5} note: pad logic 0: input 1: output bus keeper urxd0 unused dvss ? timer_a ? usart0 ? ? ? ? dv cc dv ss dv ss
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 60 post office box 655303 ? dallas, texas 75265 application information port p2, p2.1 to p2.3, input/output with schmitt trigger p2out.x module x out p2dir.x direction control from module p2sel.x d en interrupt edge select p2ies.x p2sel.x p2ie.x p2ifg.x p2irq.x en set q 0 1 1 0 pnsel.x pndir.x dir. control from module pnout.x module x out pnin.x pnie.x pnifg.x pnies.x module x in p2sel.1 p2dir.1 p2out.1 p2in.1 p2ie.1 p2ifg.1 p2ies.1 p2sel.2 p2dir.2 p2out.2 p2in.2 p2ie.2 p2ifg.2 p2ies.2 p2sel.3 p2dir.3 p2out.3 p2in.3 p2ie.3 p2ifg.3 p2ies.3 p2dir.1 p2dir.2 p2.1/tb0 p2.2/tb1 p2.3/tb2 out0 sig. module x in p2in.x 1< x< 3 note: pad logic 0: input 1: output bus keeper p2dir.3 out2 sig. out1 sig. cci0a cci0b cci1a cci1b cci2a cci2b dvss dvss module in of pin p1.3/tbouth/svsout p1sel.3 p1dir.3 ? timer_b ? ? ? ? ? ?
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 61 post office box 655303 ? dallas, texas 75265 application information port p2, p2.6 to p2.7, input/output with schmitt trigger p2out.x module x out p2dir.x direction control from module p2sel.x d en interrupt edge select p2ies.x p2sel.x p2ie.x p2ifg.x p2irq.x en set q 0 1 1 0 pnsel.x pndir.x dir. control from module pnout.x module x out pnin.x pnie.x pnifg.x pnies.x module x in 0: port active 1: segment xx function active p2sel.6 p2dir.6 p2sel.7 p2dir.7 p2dir.6 p2dir.7 p2out.6 p2out.7 p2in.6 p2in.7 unused caout adc12clk p2ie.6 p2ie.7 p2ifg.6 p2ifg.7 p2ies.6 p2ies.7 module x in p2in.x 6< x< 7 note: pad logic 0: input 1: output bus keeper unused port/lcd 0: lcdm<40h 0: lcdm<40h port /lcd ? segment xx ? p2.6/caout/s19 ? p2.7/adc12clk/s18 ? ? segment function only available with msp430x43x(1)ipn ? ? ? ? ? comparator_a ? port/lcd signal is 1 only with msp430xipn and lcdm 40h. adc12
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 62 post office box 655303 ? dallas, texas 75265 application information port p3, p3.0 to p3.3, input/output with schmitt trigger p3out.x module x out p3dir.x direction control from module p3sel.x d en 0 1 1 0 pnsel.x pndir.x pnout.x module x out pnin.x module x in p3sel.1 p3dir.1 p3out.1 p3in.1 p3sel.2 p3dir.2 p3out.2 p3in.2 p3sel.3 p3dir.3 p3out.3 p3in.3 p3sel.0 p3dir.0 p3out.0 p3in.0 uclk0(out) somio(out) dcm_simo0 dcm_somi0 dcm_uclk0 segment xx 0: port active 1: segment xx function active simo0(out) uclk0(in) somi0(in) simo0(in) ste0(in) module x in p3in.x pad logic 0: input 1: output bus keeper lcdm.5 lcdm.6 lcdm.7 direction from module control dv ss dv ss x43xipz and x44xipz have no segment p3.0/steo/s31 ? p3.1/simo0/s30 ? p3.2/somi0/s29 ? p3.3/uclk0/s28 ? function on port p3: bot h lines are low. note: 0 x 3 msp430x43x(1)ipn (80-pin) only ? s24 to s31 shared with port function only at msp430x43x(1)ipn (80-pin qfp) sync mm stc ste sync mm stc ste dcm_somi0 dcm_simo0 dcm_uclk0 direction control for somi0 direction control for simo0 and uclk0
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 63 post office box 655303 ? dallas, texas 75265 application information port p3, p3.4 to p3.7, input/output with schmitt trigger p3out.x module xout p3dir.x direction control from module p3sel.x d en 0 1 1 0 pnsel.x pndir.x dir. control from module pnout.x module x out pnin.x module x in p3sel.4 p3dir.4 p3out.4 p3in.4 p3sel.5 p3dir.5 p3out.5 p3in.5 p3dir.4 0: port active 1: segment xx function active p3sel.6 p3dir.6 p3sel.7 p3dir.7 p3out.6 p3out.7 p3in.6 p3in.7 unused cci6a unused cci5a/b unused cci4a/b unused cci3a/b module x in p3in.x 4< x< 7 note: pad logic 0: input 1: output bus keeper p3.4/s27 p3.5/s26 p3.6/s25 p3.7/s24 p3.4 p3.5 p3.6 p3.7 p3.4/tb3 p3.5/tb4 p3.6/tb5 p3.7/tb6 p3dir.5 p3dir.6 p3dir.7 dvss out3 dvss out4 dvss out5 dvss out6 module in of pin p1.3/tbouth/svsout p1sel.3 ?x43x(1)ipn ?x43x(1)ipz ?x44x(1) p3sel.x tbouthiz p1dir.3 p3dir.x lcdm.7 ? or dvss ? segmentxx ? or dvss ? tbouthiz # or dvss ? msp430x43x(1)ipn ? msp430x43x(1)ipz, msp430x44x(1)ipz msp430x43x(1) # msp430x44x(1) # # # # # # # # 80-pin 100-pin
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 64 post office box 655303 ? dallas, texas 75265 application information port p4, p4.0 to p4.7, input/output with schmitt trigger p4out.x module x out p4dir.x direction control from module p4sel.x d en 0 1 1 0 pnsel.x pndir.x pnout.x module x out pnin.x module x in p4sel.1 p4dir.1 p4out.1 p4in.1 p4sel.2 p4dir.2 p4out.2 p4in.2 p4sel.3 p4dir.3 p4out.3 p4in.3 p4sel.4 p4dir.4 p4out.4 p4in.4 p4sel.5 p4dir.5 p4out.5 p4in.5 p4sel.0 p4dir.0 p4out.0 p4in.0 segment xx 0: port active 1: segment xx function active p4sel.6 p4dir.6 p4sel.7 p4dir.7 p4dir.6 p4dir.7 p4out.6 p4out.7 p4in.6 p4in.7 unused unused unused module x in p4in.x 0< x< 7 note: pad logic 0: input 1: output bus keeper direction from module control dv ss ? utxd1 ? dv ss dv ss dv ss dv ss port /lcd x43x(1)ipn 80-pin qfp: p4.7/s2 p4.6/s3 p4.5/s4 p4.3/s6 p4.4/s5 p4.2/s7 p4.1/s8 p4.0/s9 x43x(1)ipz 100-pin qfp: p4.7/s34 p4.6/s35 p4.5/s36 p4.3/s37 p4.4/s38 p4.2/s39 p4.0 p4.1 x44x(1) p4.7/s34 p4.6/s35 p4.5/uclk1/s36 p4.4/smo1/s37 p4.3/simo1/s38 p4.2/ste1/s39 p4.1/urxd1 p4.0/utxd1 p4dir.0 ? dv cc? p4dir.1 ? dv ss? p4dir.2 ? dv ss? p4dir3. ? dcm_simo1 ? p4dir4. ? dcm_somi 1? p4dir5. ? dcm_uclk1 ? dv ss ? simo1(out ) ? dv ss ? somi1(out ) ? dv ss ? uclk1(out ) ? unused? urxd1 ? unused? ste1(in)? unused? simo1(in)? unused somi1(in)? unused? uclk1(in)? ? signal at msp430x43x(1) ? signal at msp430x44x(1) device port bits port function lcd seg. function x43x(1)ipn 80-pin qfp p4.0 . . .p4.7 lcdm < 020h lcdm 020h x43x(1)ipz 100-pin qfp p4.2 . . .p4.5 lcdm < 0e0h lcdm 0e0h x44x(1)ipz 100-pin qfp p4.6 . . .p4.7 lcdm < 0c0h lcdm 0c0h
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 65 post office box 655303 ? dallas, texas 75265 application information port p4, p4.0 to p4.7, input/output with schmitt trigger (continued) sync mm stc ste sync mm stc ste dcm_somi1 dcm_simo1 dcm_uclk1 direction control for simo1 and uclk1 direction control for somi1 port p5, p5.0 to p5.1, input/output with schmitt trigger p5out.x module x out p5dir.x direction control from module p5sel.x d en 0 1 1 0 pnsel.x pndir.x dir. control from module pnout.x module x out pnin.x module x in p5sel.1 p5dir.1 p5out.1 p5in.1 p5sel.0 p5dir.0 p5out.0 p5in.0 p5dir.1 p5dir.0 segment 0: port active 1: segment function active segment unused unused module x in p5in.x 0< x< 1 note: port pad logic 0: input 1: output bus keeper segment pad logic port/lcd port/lcd p5.0/s1 p5.1/s0 s1 s0 0: lcdm<20h 0: lcdm<20h dv ss dv ss
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 66 post office box 655303 ? dallas, texas 75265 application information port p5, p5.2 to p5.4, input/output with schmitt trigger p5out.x module x out p5dir.x direction control from module p5sel.x d en 0 1 1 0 pnsel.x pndir.x dir. control from module pnout.x module x out pnin.x module x in p5sel.2 p5dir.2 p5out.2 p5in.2 p5sel.3 p5dir.3 p5out.3 p5in.3 p5sel.4 p5dir.4 p5out.4 p5in.4 lcd signal 0: port active 1: lcd function active lcd signal unused unused unused module x in p5in.x 2< x< 4 note: pad logic 0: input 1: output bus keeper p5dir.3 p5dir.2 p5dir.4 port/lcd port/lcd p5.2/com1 p5.3/com2 p5.4/com3 com1 com2 com3 p5sel.2 p5sel.3 p5sel.4 dv ss dv ss dv ss
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 67 post office box 655303 ? dallas, texas 75265 application information port p5, p5.5 to p5.7, input/output with schmitt trigger p5out.x module x out p5dir.x direction control from module p5sel.x d en 0 1 1 0 pnsel.x pndir.x dir. control from module pnout.x module x out pnin.x module x in p5sel.5 p5dir.5 p5out.5 p5in.5 p5sel.6 p5dir.6 p5out.6 p5in.6 p5sel.7 p5dir.7 p5out.7 p5in.7 lcd signal 0: port active 1: lcd function active lcd signal unused unused unused module x in p5in.x 5< x< 7 note: pad logic 0: input 1: output bus keeper p5dir.6 p5dir.5 p5dir.7 port/lcd port/lcd r13 p5sel.5 p5.5/r13 p5.6/r23 p5.7/r33 r23 r33 p5sel.6 p5sel.7 dv ss dv ss dv ss
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 68 post office box 655303 ? dallas, texas 75265 application information port p6, p6.0 to p6.6, input/output with schmitt trigger p6.6/a6 p6in.x module x in pad logic en d p6out.x p6dir.x p6sel.x module x out direction control from module 0 1 0 1 bus keeper to adc from adc 0: input 1: output x: bit identifier, 0 to 6 for port p6 p6.0/a0 .. note: not implemented in the msp430x43x1 and msp430x44x1 devices note: analog signals applied to digital gates can cause current flow from the positive to the negative terminal. the throughput current flows if the analog signal is in the range of transitions 0 1 or 1 0. the value of the throughput current depends on the driving capability of the gate. for msp430, it is approximately 100 a. use p6sel.x=1 to prevent throughput current. p6sel.x should be set, even if the signal at the pin is not being used by the adc1 2. pnsel.x pndir.x dir. control from module pnout.x module x out pnin.x module x in p6sel.0 p6dir.0 p6dir.0 p6out.0 dv ss p6in.0 unused p6sel.1 p6dir.1 p6dir.1 p6out.1 dv ss p6in.1 unused p6sel.2 p6dir.2 p6dir.2 p6out.2 dv ss p6in.2 unused p6sel.3 p6dir.3 p6dir.3 p6out.3 dv ss p6in.3 unused p6sel.4 p6dir.4 p6dir.4 p6out.4 dv ss p6in.4 unused p6sel.5 p6dir.5 p6dir.5 p6out.5 dv ss p6in.5 unused p6sel.6 p6dir.6 p6dir.6 p6out.6 dv ss p6in.6 unused note: the signal at pins p6.x/ax is used by the 12-bit adc module.
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 69 post office box 655303 ? dallas, texas 75265 application information port p6, p6.7, input/output with schmitt trigger p6.7/a7/svsin p6in.x module x in pad logic en d p6out.x p6dir.x p6sel.x module x out direction control from module 0 1 0 1 bus keeper to adc from adc 0: input 1: output x: bit identifier, 7 for port p6 to brownout/svs module vlp(svs)=15 note: not implemented in the msp430x43x1 and msp430x44x1 devices note: analog signals applied to digital gates can cause current flow from the positive to the negative terminal. the throughput current flows if the analog signal is in the range of transitions 0 1 or 1 0. the value of the throughput current depends on the driving capability of the gate. for msp430, it is approximately 100 a. use p6sel.x=1 to prevent throughput current. p6sel.x should be set, even if the signal at the pin is not being used by the adc1 2. pnsel.x pndir.x dir. control from module pnout.x module x out pnin.x module x in p6sel.7 p6dir.7 p6dir.7 p6out.7 dv ss p6in.7 unused note: the signal at pins p6.x/ax is used by the 12-bit adc module. the signal at pin p6.7/a7/svsin is also connected to the input multiplexer in the module brownout/supply voltage supervisor.
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 70 post office box 655303 ? dallas, texas 75265 application information jtag pins tms, tck, tdi/tclk, tdo/tdi, input/output with schmitt trigger or output tdi tdo tms tdi/tclk tdo/tdi controlled by jtag tck tms tck dv cc controlled by jtag test jtag and emulation module dv cc dv cc burn and test fuse rst/nmi g d s u g d s u tck tau ~ 50 ns brownout controlled by jtag
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 71 post office box 655303 ? dallas, texas 75265 application information jtag fuse check mode msp430 devices that have the fuse on the tdi/tclk terminal have a fuse check mode that tests the continuity of the fuse the first time the jtag port is accessed after a power-on reset (por). when activated, a fuse check current (i (tf) ) of 1 ma at 3 v can flow from the tdi/tclk pin to ground if the fuse is not burned. care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. activation of the fuse check mode occurs with the first negative edge on the tms pin after power up or if the tms is being held low during power up. the second positive edge on the tms pin deactivates the fuse check mode. after deactivation, the fuse check mode remains inactive until another por occurs. after each por the fuse check mode has the potential to be activated. the fuse check current only flows when the fuse check mode is active and the tms pin is in a low state (see figure 21). therefore, the additional current flow can be prevented by holding the tms pin high (default condition). the jtag pins are terminated internally and therefore do not require external termination. time tms goes low after por tms i (tf) i tdi/tclk figure 21. fuse check mode current msp430x43x(1), msp430x44x(1)
msp430x43x1, msp430x43x, msp430x44x1, msp430x44x mixed signal microcontroller slas344g ? january 2002 ? revised october 2009 72 post office box 655303 ? dallas, texas 75265 data sheet revision history literature number summary slas344e added msp430f43x1 devices updated functional block diagram (page 6) clarified test conditions in recommended operating conditions table (page 27) clarified test conditions in electrical characteristics table (page 28) added port 2 through port 5 to leakage current table (page 29) corrected y-axis unit on figures 6 and 7; changed from v to mv (page 34) clarified test conditions in usart0/usart1 table (page 40) changed t cpt maximum value from 4 ms to 10 ms in flash memory table (page 46) slas344f added msp430f43x1 devices in pz (100 pin) package slas344g added msp430f44x1 devices note: page and figure numbers refer to the respective document revision.
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) msp430f4351ipn active lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430f4351ipnr active lqfp pn 80 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430f4351ipz active lqfp pz 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430f4351ipzr active lqfp pz 100 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430f435ipn active lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430f435ipnr active lqfp pn 80 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430f435ipz active lqfp pz 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430f435ipzr active lqfp pz 100 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430f4361ipn active lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430f4361ipnr active lqfp pn 80 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430f4361ipnrkam active lqfp pn 80 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430f4361ipz active lqfp pz 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430f4361ipzr active lqfp pz 100 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430f436ipn active lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430f436ipnr active lqfp pn 80 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430f436ipz active lqfp pz 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430f436ipzr active lqfp pz 100 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430f4371ipn active lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430f4371ipnr active lqfp pn 80 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430f4371ipz active lqfp pz 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430f4371ipzr active lqfp pz 100 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430f437ipn active lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430f437ipnr active lqfp pn 80 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430f437ipz active lqfp pz 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430f437ipzr active lqfp pz 100 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr package option addendum www.ti.com 2-oct-2009 addendum-page 1
orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) msp430f447ipz active lqfp pz 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430f447ipzr active lqfp pz 100 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr MSP430F4481IPZ active lqfp pz 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr MSP430F4481IPZr active lqfp pz 100 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430f448ipz active lqfp pz 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430f448ipzr active lqfp pz 100 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430f4491ipz active lqfp pz 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430f4491ipzr active lqfp pz 100 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430f449ipz active lqfp pz 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430f449ipzr active lqfp pz 100 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 2-oct-2009 addendum-page 2
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant msp430f447ipzr lqfp pz 100 1000 330.0 24.4 17.4 17.4 2.0 20.0 24.0 q2 MSP430F4481IPZr lqfp pz 100 1000 330.0 24.4 17.4 17.4 2.0 20.0 24.0 q2 msp430f448ipzr lqfp pz 100 1000 330.0 24.4 17.4 17.4 2.0 20.0 24.0 q2 msp430f4491ipzr lqfp pz 100 1000 330.0 24.4 17.4 17.4 2.0 20.0 24.0 q2 msp430f449ipzr lqfp pz 100 1000 330.0 24.4 17.4 17.4 2.0 20.0 24.0 q2 package materials information www.ti.com 20-oct-2010 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) msp430f447ipzr lqfp pz 100 1000 346.0 346.0 41.0 MSP430F4481IPZr lqfp pz 100 1000 346.0 346.0 41.0 msp430f448ipzr lqfp pz 100 1000 346.0 346.0 41.0 msp430f4491ipzr lqfp pz 100 1000 346.0 346.0 41.0 msp430f449ipzr lqfp pz 100 1000 346.0 346.0 41.0 package materials information www.ti.com 20-oct-2010 pack materials-page 2
mechanical data mtqf010a january 1995 revised december 1996 1 post office box 655303 ? dallas, texas 75265 pn (s-pqfp-g80) plastic quad flatpack 4040135 / b 11/96 0,17 0,27 0,13 nom 40 21 0,25 0,45 0,75 0,05 min seating plane gage plane 41 60 61 80 20 sq sq 1 13,80 14,20 12,20 9,50 typ 11,80 1,45 1,35 1,60 max 0,08 0,50 m 0,08 0 7 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026
mechanical data mtqf013a october 1994 revised december 1996 1 post office box 655303 ? dallas, texas 75265 pz (s-pqfp-g100) plastic quad flatpack 4040149 /b 11/96 50 26 0,13 nom gage plane 0,25 0,45 0,75 0,05 min 0,27 51 25 75 1 12,00 typ 0,17 76 100 sq sq 15,80 16,20 13,80 1,35 1,45 1,60 max 14,20 0 7 seating plane 0,08 0,50 m 0,08 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of ti information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. information of third parties may be subject to additional restrictions. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. ti products are not authorized for use in safety-critical applications (such as life support) where a failure of the ti product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of ti products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by ti. further, buyers must fully indemnify ti and its representatives against any damages arising out of the use of ti products in such safety-critical applications. ti products are neither designed nor intended for use in military/aerospace applications or environments unless the ti products are specifically designated by ti as military-grade or "enhanced plastic." only products designated by ti as military-grade meet military specifications. buyers acknowledge and agree that any such use of ti products which ti has not designated as military-grade is solely at the buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. ti products are neither designed nor intended for use in automotive applications or environments unless the specific ti products are designated by ti as compliant with iso/ts 16949 requirements. buyers acknowledge and agree that, if they use any non-designated products in automotive applications, ti will not be responsible for any failure to meet such requirements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dlp? 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